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    PROCESS-VOLTAGE-TEMPERATURE TOLERANT REPLICA FEEDBACK PULSE GENERATOR CIRCUIT FOR PULSED LATCH
    11.
    发明公开
    PROCESS-VOLTAGE-TEMPERATURE TOLERANT REPLICA FEEDBACK PULSE GENERATOR CIRCUIT FOR PULSED LATCH 审中-公开

    公开(公告)号：US20240223167A1

    公开(公告)日：2024-07-04

    申请号：US18091970

    申请日：2022-12-30

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven K. Hsu ,  Mark A. Anders ,  Ram K. Krishnamurthy

    IPC: H03K4/94 ,  H03K3/037

    CPC classification number: H03K4/94 ,  H03K3/037 ,  H03K19/20

    Abstract: Embodiments herein relate to a pulse generator which provides first and second clock pulses to one or more pulsed latches, where the pulse generator replicates a delay of the pulsed latches in providing the first and second clock pulses. The pulse generator can include a replica of latch components in the pulsed latches such as a tri-state inverter, a transmission gate and inverters, where an output of the tri-state inverter is coupled to the transmission gate and to an input of the inverter, and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter can be a modified tri-state inverter with an output forced to “1” when a clock signal is “0.” In one approach, the latch components of the pulse generator are to write a logic 1 when a clock signal goes high.

    High performance fast Mux-D scan flip-flop
    12.
    发明授权
    High performance fast Mux-D scan flip-flop 有权

    公开(公告)号：US11296681B2

    公开(公告)日：2022-04-05

    申请号：US16726020

    申请日：2019-12-23

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven Hsu ,  Simeon Realov ,  Mahesh Kumashikar ,  Ram Krishnamurthy

    IPC: H03K3/00 ,  H03K3/037 ,  G01R31/3177 ,  H03K3/038 ,  H03K19/20

    Abstract: A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

    HIGH PERFORMANCE FAST MUX-D SCAN FLIP-FLOP
    14.
    发明申请
    HIGH PERFORMANCE FAST MUX-D SCAN FLIP-FLOP 有权

    公开(公告)号：US20210194469A1

    公开(公告)日：2021-06-24

    申请号：US16726020

    申请日：2019-12-23

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven Hsu ,  Simeon Realov ,  Mahesh Kumashikar ,  Ram Krishnamurthy

    IPC: H03K3/037 ,  H03K19/20 ,  H03K3/038 ,  G01R31/3177

    Abstract: A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

    PATTERN MATCHING CIRCUIT
    17.
    发明申请
    PATTERN MATCHING CIRCUIT 审中-公开

    公开(公告)号：US20170286420A1

    公开(公告)日：2017-10-05

    申请号：US15085816

    申请日：2016-03-30

    Applicant: Intel Corporation

    Inventor： Amit Agarwal ,  Steven K. Hsu ,  Kaushik Vaidyanathan ,  Ram K. Krishnamurthy

    IPC: G06F17/30 ,  G06F21/56

    CPC classification number: G06F16/9014 ,  Y02D10/45

    Abstract: Embodiments include a pattern matching circuit that implements a Bloom filter including one or more hash functions. The hash functions may generate respective addresses corresponding to bits of a memory array. Various techniques for improving the area and/or power efficiency of the pattern matching circuit are disclosed. For example, a number of logic 1 bits per column of hash matrixes associated with the one or more hash functions may be restricted to a pre-defined number. A plurality of addresses generated by the hash functions may use the same column address to correspond to bits of a same column. A single read port memory may be used to simultaneously read two bits and generate an output signal that indicates whether the two bits are both a first logic value. Other embodiments may be described and claimed.

    INTEGRATED CLOCK GATE WITH CIRCUITRY TO FACILITATE CLOCK FREQUENCY DIVISION
    18.
    发明公开
    INTEGRATED CLOCK GATE WITH CIRCUITRY TO FACILITATE CLOCK FREQUENCY DIVISION 审中-公开

    公开(公告)号：US20240007087A1

    公开(公告)日：2024-01-04

    申请号：US17856887

    申请日：2022-07-01

    Applicant: Intel Corporation

    Inventor： Steven Hsu ,  Amit Agarwal ,  Simeon Realov ,  Mark Anders ,  Ram Krishnamurthy

    IPC: H03K3/037 ,  H03K19/21 ,  G06F1/06

    CPC classification number: H03K3/037 ,  H03K19/21 ,  G06F1/06

    Abstract: Techniques and mechanisms for an integrated clock gate (ICG) to selectively output a clock signal, and to provide frequency division functionality. In an embodiment, an ICG circuit comprises first circuitry which is coupled to receive a first clock signal, and second circuitry which is coupled to receive a control signal. The first circuitry provides a single edge triggered flip-flop functionality, and is coupled to communicate a feedback signal which the first circuitry is further coupled to receive. Based on the control signal and the feedback signal, the second circuitry performs an exclusive OR (XOR) operation to selectively enable the first circuitry to generate a second clock signal based on the first clock signal. In another embodiment, a frequency of the second clock signal is substantially equal to one half of a frequency of the first clock signal.

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