公开(公告)号：US20180293965A1

公开(公告)日：2018-10-11

申请号：US15482535

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： BALAJI VEMBU ,  JASON TANNER ,  JOYDEEP RAY ,  ALTUG KOKER ,  ABHISHEK R. APPU ,  PATTABHIRAMAN K

IPC: G09G5/395 ,  G06F9/455 ,  G06T1/60 ,  G09G5/36 ,  G06T15/00 ,  H04N19/42 ,  G06T1/20 ,  G06T9/00

CPC classification number: G09G5/395 ,  G06F3/1423 ,  G06F9/452 ,  G06F9/45533 ,  G06T1/20 ,  G06T1/60 ,  G06T9/004 ,  G06T15/005 ,  G09G3/003 ,  G09G5/36 ,  G09G5/363 ,  G09G2340/02 ,  G09G2352/00 ,  G09G2360/08 ,  G09G2360/121 ,  G09G2370/022 ,  H04N19/42

Abstract: An apparatus and method are described for efficiently rendering an transmitting to a remote display. For example, one embodiment of a remote display apparatus comprises: a display engine to render a sequence of video images; an encoder to compress the sequence of video images to generate a sequence of compressed video images; a network interface controller to transmit the compressed video images over a network link to a remote display; a plurality of buffer pointer registers to store read pointers and write pointers identifying read locations and write locations, respectively, in a frame buffer and a compressed stream buffer; a central processing unit (CPU) to initialize the read pointers and write pointers for processing one or more of the video images; and the display engine to access a first write pointer to write to a specified location in the frame buffer, the encoder to begin reading from the frame buffer based on a first read pointer value, the encoder to write to the compressed stream buffer based on a second write pointer value, and the network interface controller to read from the compressed stream buffer based on a second read pointer value, the first and second write and read pointer values to be updated without intervention from the CPU as the display engine writes to the frame buffer, the encoder reads from the frame buffer and writes to the compressed stream buffer, and the network interface controller reads from the compressed stream buffer.

公开(公告)号：US20180012328A1

公开(公告)日：2018-01-11

申请号：US15204402

申请日：2016-07-07

Applicant: Intel Corporation

Inventor： Jeffery S. Boles ,  HEMA C. NALLURI ,  BALAJI VEMBU ,  PRITAV H. SHAH ,  MICHAEL APODACA ,  MURALI RAMADOSS ,  LALIT K. SAPTARSHI

IPC: G06T1/60 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06T1/20

Abstract: A mechanism for command stream processing is described. A method of embodiments, as described herein, includes fetching cache lines from a memory to fill command first in first out buffer (FIFO), wherein the fetched cachelines an overfetching of data necessary to process a command, a first parser to fetch and execute batch commands stored in the command FIFO and a second parser to fetch commands and execute the batch commands and non-batch commands stored in the command FIFO.

公开(公告)号：US20170347065A1

公开(公告)日：2017-11-30

申请号：US15169262

申请日：2016-05-31

Applicant: Intel Corporation

Inventor： VIDHYA KRISHNAN ,  BALAJI VEMBU ,  SANDEEP S. SODHI ,  PRIYADARSINI DEVANAND

IPC: H04N7/167 ,  H04L9/06

CPC classification number: H04N7/1675 ,  H04L9/065 ,  H04L2209/125 ,  H04L2209/34 ,  H04L2209/60 ,  H04N21/2347

Abstract: Apparatuses, methods and storage medium associated with single pass parallel encryption are disclosed herein. In embodiments, an apparatus for computing may comprise an encryption engine to encrypt a video stream. The encryption engine may comprise a plurality of encryption pipelines to respectively encrypt a plurality of video sub-streams partitioned from the video stream in parallel in a single pass as the video sub-streams are being generated. The plurality of encryption pipelines may use a corresponding plurality of multi-part encryption counters to encrypt the corresponding video sub-streams as the video sub-streams are being generated. Each of the multi-part encryption counters used by one of the encryption pipelines may comprise a sub-portion that remains constant while encoding the corresponding video sub-stream, but the sub-key is unique for the one encryption pipeline, and differs from corresponding sub-portions of the multi-part encryption counters used by the other encryption pipelines. Other embodiments may be disclosed or claimed.

公开(公告)号：US20160239333A1

公开(公告)日：2016-08-18

申请号：US15025735

申请日：2013-11-27

Applicant: INTEL CORPORATION

Inventor： DAVID J. COWPERTHWAITE ,  MURALI RAMADOSS ,  ANKUR N. SHAH ,  BALAJI VEMBU ,  ALTUG KOKER ,  ADITYA NAVALE

IPC: G06F9/455 ,  G06T1/20

CPC classification number: G06F9/45558 ,  G06F9/5044 ,  G06F9/5077 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06T1/20 ,  G06T2200/28

Abstract: In an embodiment, a system includes a graphics processing unit (GPU) that includes one or more GPU engines, and a microcontroller. The microcontroller is to assign a respective schedule slot for each of a plurality of virtual machines (VMs). When a particular VM is scheduled to access a first GPU engine, the particular VM has exclusive access to the first GPU engine. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，系统包括包括一个或多个GPU引擎的图形处理单元（GPU）和微控制器。 微控制器将为多个虚拟机（VM）中的每一个分配相应的调度时隙。 当特定VM被安排访问第一GPU引擎时，特定VM具有对第一GPU引擎的独占访问。 描述和要求保护其他实施例。

公开(公告)号：US20210056051A1

公开(公告)日：2021-02-25

申请号：US17008991

申请日：2020-09-01

Applicant: Intel Corporation

Inventor： NIRANJAN L. COORAY ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  JOYDEEP RAY ,  BALAJI VEMBU ,  PATTABHIRAMAN K ,  DAVID PUFFER ,  DAVID J. COWPERTHWAITE ,  RAJESH M. SANKARAN ,  SATYESHWAR SINGH ,  SAMEER KP ,  ANKUR N. SHAH ,  KUN TIAN

IPC: G06F13/16 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/0802 ,  G06F13/40

Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

公开(公告)号：US20200210246A1

公开(公告)日：2020-07-02

申请号：US16696848

申请日：2019-11-26

Applicant: Intel Corporation

Inventor： PRASOONKUMAR SURTI ,  DAVID COWPERTHWAITE ,  ABHISHEK R. APPU ,  JOYDEEP RAY ,  VASANTH RANGANATHAN ,  ALTUG KOKER ,  BALAJI VEMBU

IPC: G06F9/50

Abstract: A mechanism is described for facilitating localized load-balancing for processors in computing devices. A method of embodiments, as described herein, includes facilitating hosting, at a processor of a computing device, a local load-balancing mechanism. The method may further include monitoring balancing of loads at the processor and serving as a local scheduler to maintain de-centralized load-balancing at the processor and between the processor and other one or more processors.

公开(公告)号：US20180308195A1

公开(公告)日：2018-10-25

申请号：US15493233

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： BALAJI VEMBU ,  ALTUG KOKER ,  JOYDEEP RAY

IPC: G06T1/20 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06T15/005 ,  G06T2200/04

Abstract: One embodiment provides for a general-purpose graphics processing unit comprising multiple processing units and a pipeline manager to distribute a thread group to the multiple processing units, wherein the pipeline manager is to distribute the thread group as multiple thread sub-groups.

公开(公告)号：US20180293776A1

公开(公告)日：2018-10-11

申请号：US15482677

申请日：2017-04-07

Applicant: Intel Corporation

Inventor： JOYDEEP RAY ,  ABHISHEK R. APPU ,  PATTABHIRAMAN K ,  BALAJI VEMBU ,  ALTUG KOKER ,  NIRANJAN L. COORAY ,  JOSH B. MASTRONARDE

IPC: G06T15/00 ,  G06F9/455 ,  G06F9/48 ,  G06F9/50

Abstract: An apparatus and method are described for allocating local memories to virtual machines. For example, one embodiment of an apparatus comprises: a command streamer to queue commands from a plurality of virtual machines (VMs) or applications, the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU); a tile cache to store graphics data associated with the plurality of VMs or applications as the commands are executed by the graphics processing resources; and tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM or application and a second portion of the tile cache to a second VM or application; the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data when the first portion of the tile cache and/or the second portion of the file cache becomes full.

公开(公告)号：US20180286009A1

公开(公告)日：2018-10-04

申请号：US15992642

申请日：2018-05-30

Applicant: Intel Corporation

Inventor： JEFFERY S. BOLES ,  HEMA C. NALLURI ,  BALAJI VEMBU ,  MICHAEL APODACA ,  ALTUG KOKER ,  LALIT K. SAPTARSHI

IPC: G06T1/20 ,  G06F3/06 ,  G06F12/0846 ,  G06T1/60 ,  G09G5/36

Abstract: In accordance with some embodiments, a command streamer may use a cache of programmable size to cache commands to improve memory bandwidth and reduce latency. The size of the command cache may be programmably set by the command streamer.