公开(公告)号：US10461082B2

公开(公告)日：2019-10-29

申请号：US15577734

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Chandra S. Mohapatra ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Nadia M. Rahhal-Orabi ,  Tahir Ghani

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/8258 ,  H01L29/10

Abstract: Non-silicon fin structures extend from a crystalline heteroepitaxial well material in a well recess of a substrate. III-V finFETs may be formed on the fin structures within the well recess while group IV finFETs are formed in a region of the substrate adjacent to the well recess. The well material may be electrically isolated from the substrate by an amorphous isolation material surrounding pillars passing through the isolation material that couple the well material to a seeding surface of the substrate and trap crystal growth defects. The pillars may be expanded over the well-isolation material by lateral epitaxial overgrowth, and the well recess filled with a single crystal of high quality. Well material may be planarized with adjacent substrate regions. N-type fin structures may be fabricated from the well material in succession with p-type fin structures fabricated from the substrate, or second epitaxial well.

公开(公告)号：US10411007B2

公开(公告)日：2019-09-10

申请号：US15755490

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Matthew V. Metz ,  Chandra S. Mohapatra ,  Sean T. Ma ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L27/06 ,  H01L29/66 ,  H01L21/8252 ,  H01L29/775 ,  H01L29/06 ,  H01L29/205 ,  H01L21/8258 ,  H01L29/16 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  B82Y10/00 ,  H01L27/092 ,  H01L21/8238

Abstract: Monolithic FETs including a channel region in a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a channel region, a semiconductor spacer of a semiconductor material with a band offset relative to the channel material is grown, for example on at least a drain end of the channel region to introduce at least one charge carrier-blocking band offset between the channel semiconductor and a drain region of a third III-V semiconductor material. In some N-type transistor embodiments, the carrier-blocking band offset is a conduction band offset of at least 0.1 eV. A wider band gap and/or a blocking conduction band offset may contribute to reduced gate induced drain leakage (GIDL). Source/drain regions couple electrically to the channel region through the semiconductor spacer, which may be substantially undoped (i.e. intrinsic) or doped. In some embodiments, the semiconductor spacer growth is integrated into a gate-last, source/drain regrowth finFET fabrication process.

公开(公告)号：US10373977B2

公开(公告)日：2019-08-06

申请号：US15576393

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Daniel B. Aubertine ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Chandra S. Mohapatra ,  Karthik Jambunathan ,  Gilbert Dewey ,  Willy Rachmady

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/84 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced. The sacrificial fins can be thought of as cores and can be implemented, for example, with material native to the substrate or a replacement material that enables low-defect exotic cladding materials combinations.

公开(公告)号：US20180248028A1

公开(公告)日：2018-08-30

申请号：US15755489

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Chandra S. Mohapatra ,  Matthew V. Metz ,  Harold W. Kennel ,  Gilbert Dewey ,  Willy Rachmady ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/02 ,  H01L29/778 ,  H01L27/092

CPC classification number: H01L29/785 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02455 ,  H01L21/02494 ,  H01L21/02538 ,  H01L21/02639 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/778

Abstract: III-V compound semiconductor devices, such transistors, may be formed in active regions of a III-V semiconductor material disposed over a silicon substrate. A heterojunction between an active region of III-V semiconductor and the substrate provides a diffusion barrier retarding diffusion of silicon from the substrate into III-V semiconductor material where the silicon might otherwise behave as an electrically active amphoteric contaminate. In some embodiments, the heterojunction is provided within a base portion of a sub-fin disposed between the substrate and a fin containing a transistor channel region. The heterojunction positioned closer to the substrate than active fin region ensures thermal diffusion of silicon atoms is contained away from the active region of a III-V finFET.

公开(公告)号：US11764275B2

公开(公告)日：2023-09-19

申请号：US16074373

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Chandra S. Mohapatra ,  Glenn A. Glass ,  Harold W. Kennel ,  Anand S. Murthy ,  Willy Rachmady ,  Gilbert Dewey ,  Sean T. Ma ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/417 ,  H01L29/201 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L29/201 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: An apparatus including a transistor device disposed on a surface of a circuit substrate, the device including a body including opposing sidewalls defining a width dimension and a channel material including indium, the channel material including a profile at a base thereof that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body including opposing sidewalls and including a buffer material and a channel material on the buffer material, the channel material including indium and the buffer material includes a facet that promotes indium atom diffusivity changes in the channel material in a direction away from the sidewalls; and forming a gate stack on the channel material.

公开(公告)号：US20220181442A1

公开(公告)日：2022-06-09

申请号：US17677859

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Matthew V. Metz ,  Willy Rachmady ,  Gilbert Dewey ,  Chandra S. Mohapatra ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/8258 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78

Abstract: Monolithic FETs including a fin of a first semiconductor composition disposed on a sub-fin of a second composition. In some examples, an InGaAs fin is grown over GaAs sub-fin. The sub-fin may be epitaxially grown from a seeding surface disposed within a trench defined in an isolation dielectric. The sub-fin may be planarized with the isolation dielectric. The fin may then be epitaxially grown from the planarized surface of the sub-fin. A gate stack may be disposed over the fin with the gate stack contacting the planarized surface of the isolation dielectric so as to be self-aligned with the interface between the fin and sub-fin. Other embodiments may be described and/or claimed.

公开(公告)号：US10797150B2

公开(公告)日：2020-10-06

申请号：US15770468

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Willy Rachmady ,  Matthew V. Metz ,  Chandra S. Mohapatra ,  Gilbert Dewey ,  Nadia M. Rahhal-Orabi ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L29/00 ,  H01L29/49 ,  H01L29/78 ,  H01L29/10 ,  H01L21/28 ,  H01L29/205 ,  H01L29/66

Abstract: An apparatus including a non-planar body on a substrate, the body including a channel on a blocking material, and a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel material and a second gate electrode material including a second work function different from the first work function disposed on the channel material and on the blocking material. A method including forming a non-planar body on a substrate, the non-planar body including a channel on a blocking material, and forming a gate stack on the body, the gate stack including a first gate electrode material including a first work function disposed on the channel and a second gate electrode material including a second work function different from the first work function disposed on the channel and on the blocking material.

公开(公告)号：US10749032B2

公开(公告)日：2020-08-18

申请号：US16076550

申请日：2016-03-11

Applicant: INTEL CORPORATION

Inventor： Chandra S. Mohapatra ,  Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Willy Rachmady ,  Gilbert Dewey ,  Tahir Ghani ,  Jack T. Kavalieros

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/775 ,  B82Y10/00 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8252 ,  H01L27/092 ,  H01L29/20

Abstract: Techniques are disclosed for forming transistors including one or more group III-V semiconductor material nanowires using sacrificial group IV semiconductor material layers. In some cases, the transistors may include a gate-all-around (GAA) configuration. In some cases, the techniques may include forming a replacement fin stack that includes group III-V material layer (such as indium gallium arsenide, indium arsenide, or indium antimonide) formed on a group IV material buffer layer (such as silicon, germanium, or silicon germanium), such that the group IV buffer layer can be later removed using a selective etch process to leave the group III-V material for use as a nanowire in a transistor channel. In some such cases, the group III-V material layer may be grown pseudomorphically to the underlying group IV material, so as to not form misfit dislocations. The techniques may be used to form transistors including any number of nanowires.

公开(公告)号：US10546858B2

公开(公告)日：2020-01-28

申请号：US15579180

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Jack T. Kavalieros ,  Chandra S. Mohapatra ,  Anand S. Murthy ,  Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Tahir Ghani ,  Harold W. Kennel

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/78 ,  H01L27/06 ,  H01L21/306 ,  H01L29/66 ,  H01L21/225 ,  H01L21/324 ,  H01L21/8258 ,  H01L29/205 ,  H01L29/207

Abstract: Monolithic finFETs including a majority carrier channel in a first III-V compound semiconductor material disposed on a second III-V compound semiconductor. While a mask, such as a sacrificial gate stack, is covering the channel region, a source of an amphoteric dopant is deposited over exposed fin sidewalls and diffused into the first III-V compound semiconductor material. The amphoteric dopant preferentially activates as a donor within the first III-V material and an acceptor with the second III-V material, providing transistor tip doping with a p-n junction between the first and second III-V materials. A lateral spacer is deposited to cover the tip portion of the fin. Source/drain regions in regions of the fin not covered by the mask or spacer electrically couple to the channel through the tip region. The channel mask is replaced with a gate stack.

公开(公告)号：US10529808B2

公开(公告)日：2020-01-07

申请号：US16072313

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Chandra S. Mohapatra ,  Harold W. Kennel ,  Glenn A. Glass ,  Will Rachmady ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani ,  Matthew V. Metz ,  Sean T. Ma

IPC: H01L29/417 ,  H01L29/205 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: An apparatus including a transistor device on a substrate including an intrinsic layer including a channel; a source and a drain on opposite sides of the channel; and a diffusion barrier between the intrinsic layer and each of the source and the drain, the diffusion barrier including a conduction band energy that is less than a conduction band energy of the channel and greater than a material of the source and drain. A method including defining an area of an intrinsic layer on a substrate for a channel of a transistor device; forming a diffusion barrier layer in an area defined for a source and a drain; and forming a source on the diffusion barrier layer in the area defined for the source and forming a drain in the area defined for the drain.