公开(公告)号：US09824037B2

公开(公告)日：2017-11-21

申请号：US14882824

申请日：2015-10-14

Applicant: Intel Corporation

Inventor： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC: G06F13/20 ,  G06F12/0806 ,  G06F12/06 ,  G06F12/02 ,  G06F3/06 ,  G06F13/28 ,  G06F13/40 ,  G06F15/76 ,  G06F15/173 ,  G11C7/10 ,  G06F12/10 ,  G06F12/109

CPC classification number: G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

公开(公告)号：US20150081999A1

公开(公告)日：2015-03-19

申请号：US14286055

申请日：2014-05-23

Applicant: Intel Corporation

Inventor： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC: G06F12/02

CPC classification number: G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

Abstract translation: 一般来说，本公开包括具有集成在处理器内的多个可编程单元的装置。 该装置具有将单个地址空间中的地址映射到多个可编程单元内的资源的电路，其中单个地址空间包括针对多个可编程单元中的不同可编程单元中的不同资源的地址，并且其中存在一对一 单个地址空间中的各个地址与多个可编程单元内的资源之间的对应关系。

公开(公告)号：US12021551B2

公开(公告)日：2024-06-25

申请号：US17133609

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： James Guilford ,  Vinodh Gopal ,  Daniel Cutter ,  Kirk Yap

IPC: H03M7/34 ,  G06F3/06 ,  G11C15/00 ,  H03M7/30 ,  H03M7/40

CPC classification number: H03M7/40 ,  G06F3/0608 ,  G06F3/0638 ,  G06F3/0673 ,  G11C15/00 ,  H03M7/3086

Abstract: Apparatus and method for efficient compression block decoding using content-addressable structure for header processing. For example, one embodiment of an apparatus comprises: a header parser to extract a sequence of tokens and corresponding length values from a header of a compression block, the tokens and corresponding length values associated with a type of compression used to compress a payload of the compression block; and a content-addressable data structure builder to construct a content-addressable data structure based on the tokens and length values, the content-addressable data structure builder to write an entry in the content-addressable data structure comprising a length value and a count value, the count value indicating a number of times the length value was previously written to an entry in the content-addressable data structure.

公开(公告)号：US11955995B2

公开(公告)日：2024-04-09

申请号：US16872144

申请日：2020-05-11

Applicant: Intel Corporation

Inventor： James Guilford ,  Vinodh Gopal ,  Daniel Cutter ,  Kirk Yap ,  Wajdi Feghali ,  George Powley

IPC: H03M7/30 ,  H03M7/46

CPC classification number: H03M7/607 ,  H03M7/3066 ,  H03M7/3084 ,  H03M7/46

Abstract: A lossless data compressor of an aspect includes a first lossless data compressor circuitry coupled to receive input data. The first lossless data compressor circuitry is to apply a first lossless data compression approach to compress the input data to generate intermediate compressed data. The apparatus also includes a second lossless data compressor circuitry coupled with the first lossless data compressor circuitry to receive the intermediate compressed data. The second lossless data compressor circuitry is to apply a second lossless data compression approach to compress at least some of the intermediate compressed data to generate compressed data. The second lossless data compression approach different than the first lossless data compression approach. Lossless data decompressors are also disclosed, as are methods of lossless data compression and decompression.

公开(公告)号：US09830285B2

公开(公告)日：2017-11-28

申请号：US14882867

申请日：2015-10-14

Applicant: Intel Corporation

Inventor： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC: G06F13/20 ,  G06F12/0806 ,  G06F12/06 ,  G06F12/02 ,  G06F3/06 ,  G06F13/28 ,  G06F13/40 ,  G06F15/76 ,  G06F15/173 ,  G11C7/10 ,  G06F12/10 ,  G06F12/109

CPC classification number: G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

公开(公告)号：US09824038B2

公开(公告)日：2017-11-21

申请号：US14882897

申请日：2015-10-14

Applicant: Intel Corporation

Inventor： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC: G06F13/20 ,  G06F12/0806 ,  G06F12/06 ,  G06F12/02 ,  G06F3/06 ,  G06F13/28 ,  G06F13/40 ,  G06F15/76 ,  G06F15/173 ,  G11C7/10 ,  G06F12/10 ,  G06F12/109

CPC classification number: G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

公开(公告)号：US09128818B2

公开(公告)日：2015-09-08

申请号：US14286055

申请日：2014-05-23

Applicant: Intel Corporation

Inventor： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/10

CPC classification number: G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

Abstract: The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

Abstract translation: 一般来说，本公开包括具有集成在处理器内的多个可编程单元的装置。 该装置具有将单个地址空间中的地址映射到多个可编程单元内的资源的电路，其中单个地址空间包括针对多个可编程单元中的不同可编程单元中的不同资源的地址，并且其中存在一对一 单个地址空间中的各个地址与多个可编程单元内的资源之间的对应关系。

公开(公告)号：US11243836B2

公开(公告)日：2022-02-08

申请号：US16908686

申请日：2020-06-22

Applicant: INTEL CORPORATION

Inventor： Vinodh Gopal ,  James Guilford ,  Daniel Cutter ,  Kirk Yap

IPC: G06F11/10 ,  H03M7/30 ,  H03M7/40

Abstract: A processing device comprising compression circuitry to: determine a compression configuration to compress source data; generate a checksum of the source data in an uncompressed state; compress the source data into at least one block based on the compression configuration, wherein the at least one block comprises: a plurality of sub-blocks, wherein the plurality of sub-block includes a predetermined size; a block header corresponding to the plurality of sub-blocks; and decompression circuitry coupled to the compression circuitry, wherein the decompression circuitry to: while not outputting a decompressed data stream of the source data: generate index information corresponding to the plurality of sub-blocks; in response to generating the index information, generate a checksum of the compressed source data associated with the plurality of sub-blocks; and determine whether the checksum of the source data in the uncompressed format matches the checksum of the compressed source data.

公开(公告)号：US11095305B1

公开(公告)日：2021-08-17

申请号：US16391246

申请日：2019-04-22

Applicant: Intel Corporation

Inventor： James Guilford ,  Kirk Yap ,  Vinodh Gopal ,  Daniel Cutter ,  Wajdi Feghali

IPC: H03M7/34 ,  H03M7/30 ,  H03M7/40

Abstract: An apparatus and method for performing efficient lossless compression. For example, one embodiment of an apparatus comprises: first compression circuitry to identify and replace one or more repeated bit strings from an input data stream with distances to the one or more repeated bit strings, the first compression circuitry to generate a first compressed data stream comprising literal-length data identifying a first instance of each repeated bit string and distance data comprising distances from the first instance to each repeated instance of the repeated bit string; second compression circuitry to perform sorting, tree generation, and length calculations for literal-length values and distance values of the first compressed data stream, the second compression circuitry comprising: variable length code mapping circuitry to map each literal-length value and distance value to a variable length code; header generation circuitry to generate a header for a final compressed bit stream using the length calculations; and a transcoder to substitute the variable length codes in place of the literal-length and distance values to generate a compressed bit stream body, wherein the transcoder operates in parallel with the header generation circuitry; and bit stream merge circuitry to combine the header with the compressed bit stream body to generate a final lossless compressed bitstream.

公开(公告)号：US20190034490A1

公开(公告)日：2019-01-31

申请号：US15856858

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Kirk Yap ,  James Guilford ,  Daniel Cutter ,  Vinodh Gopal

IPC: G06F17/30

Abstract: Technologies for determining set membership include a computing device that further includes one or more accelerator devices. Each accelerator device is to receive input data and definition table configuration data, the input data including a packed unsigned integers of column data from database and the definition table configuration data including a set membership query condition, generate a definition table indicative of element values that satisfy the set membership query condition, generate a lookup request for an element of the column data of the input data, perform the lookup request by accessing the definition table to determine whether the element satisfies the set membership query condition, and generate output indicative of whether the element is a member of the set membership.