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    Flow control with reduced buffer usage for network devices
    11.
    发明授权
    Flow control with reduced buffer usage for network devices 有权
    流量控制，减少网络设备的缓冲区使用量

    公开(公告)号：US09030936B2

    公开(公告)日：2015-05-12

    申请号：US13915857

    申请日：2013-06-12

    Applicant: Intel Corporation

    Inventor： Ben-zion Friedman ,  Eliezer Tamir

    IPC: G01R31/08 ,  H04L12/823

    CPC classification number: H04L47/32 ,  H04L47/245 ,  H04L47/39

    Abstract: Methods and apparatus for implementing flow control with reduced buffer usage for network devices. In response to detection of flow control events, transmission of a data unit or segment such as an Ethernet frame is preempted in favor of a flow control message, resulting in aborting transmission of the frame. Data corresponding to the entirety of the frame is buffered at the transmitting station until the frame has been transmitted (or after a delay), enabling retransmission of the aborted frame. Preemption of frames in favor of flow control messages results in earlier responses to flow control events, enabling the size of buffers to be reduced.

    Abstract translation: 用于实现流量控制的方法和装置，减少网络设备的缓冲区使用。 响应于流量控制事件的检测，诸如以太网帧之类的数据单元或段的传输被抢占有利于流控制消息，导致中止帧的传输。 对应于整个帧的数据在发送站处被缓冲，直到该帧已经被发送（或者在一个延迟之后），使得重新发送中止的帧。 支持流控制消息的帧的抢占导致对流控制事件的早期响应，使得能够减少缓冲器的大小。

    SYSTEMS AND METHODS FOR MULTI-ARCHITECTURE COMPUTING
    14.
    发明申请
    SYSTEMS AND METHODS FOR MULTI-ARCHITECTURE COMPUTING 有权

    公开(公告)号：US20220197851A1

    公开(公告)日：2022-06-23

    申请号：US17693696

    申请日：2022-03-14

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Ben-Zion Friedman

    IPC: G06F15/173 ,  G06F11/14 ,  G06F9/48 ,  G06F15/76 ,  G06F11/30

    Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing system may include: a processor system including at least one first processor core having a first instruction set architecture (ISA); a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA; and control logic to suspend execution of the program by the at least one first processor core and cause at least one second processor core to resume execution of the program, wherein the at least one second processor core has a second ISA different from the first ISA; wherein the program is to generate data having an in-memory representation compatible with both the first ISA and the second ISA.

    Systems and methods for multi-architecture computing
    15.
    发明授权
    Systems and methods for multi-architecture computing 有权

    公开(公告)号：US11275709B2

    公开(公告)日：2022-03-15

    申请号：US15584343

    申请日：2017-05-02

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Ben-Zion Friedman

    IPC: G06F15/173 ,  G06F11/14 ,  G06F9/48 ,  G06F15/76 ,  G06F11/30 ,  H04L29/08 ,  G06F9/455 ,  H04L67/1001

    Abstract: Disclosed herein are systems and methods for multi-architecture computing. For example, in some embodiments, a computing system may include: a processor system including at least one first processor core having a first instruction set architecture (ISA); a memory device coupled to the processor system, wherein the memory device has stored thereon a first binary representation of a program for the first ISA; and control logic to suspend execution of the program by the at least one first processor core and cause at least one second processor core to resume execution of the program, wherein the at least one second processor core has a second ISA different from the first ISA; wherein the program is to generate data having an in-memory representation compatible with both the first ISA and the second ISA.

    Active link during LAN interface reset
    16.
    发明授权
    Active link during LAN interface reset 有权

    公开(公告)号：US11134125B2

    公开(公告)日：2021-09-28

    申请号：US15749645

    申请日：2016-09-23

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Ben-Zion Friedman ,  Itamar Levin

    IPC: H04L12/851 ,  H04L29/06 ,  H04L29/08 ,  H04L12/24 ,  H04L12/861 ,  H04L12/835 ,  H04L12/825 ,  H04L12/28

    Abstract: Methods and apparatus for supporting active link status during LAN interface reset and reconfigurations. Under one aspect, during normal operations traffic is transmitted over an Ethernet link coupling a first link partner to a second link partner. In response to a network interface re-configuration event, transmission of traffic over the Ethernet link is paused while keeping the Physical layer (PHY) of the Ethernet link active. The configuration of the first link partner is updated while the transmission of traffic is paused and the PHY of the Ethernet link is active. Upon completion of the configuration update, the link partners resume transmission of traffic over the Ethernet link. Additional schemes are provided that support re-configuration of network interfaces that support link and per priority flow control. According to another aspect, separate power domains are used for the PHY and the MAC circuitry, enabling the MAC circuitry to be reset via a power cycle while maintaining power to the PHY circuitry.

    VIRTUAL MACHINE MIGRATION WHILE MAINTAINING LIVE NETWORK LINKS
    17.
    发明申请
    VIRTUAL MACHINE MIGRATION WHILE MAINTAINING LIVE NETWORK LINKS 有权

    公开(公告)号：US20210117224A1

    公开(公告)日：2021-04-22

    申请号：US17134305

    申请日：2020-12-26

    Applicant: Intel Corporation

    Inventor： Stephen T. Palermo ,  Krishnamurthy Jambur Sathyanarayana ,  Sean Harte ,  Thomas Long ,  Eliezer Tamir ,  Hari K. Tadepalli

    IPC: G06F9/455 ,  H04L29/08

    Abstract: Disclosed is a source host including a processor. The processor operates a virtual machine (VM) to communicate network traffic over a communication link. The processor also initiates migration of the VM to a destination host. The processor also suspends the VM during migration of the VM to the destination host. The source host also includes a live migration circuit coupled to the processor. The live migration circuit manages a session associated with the communication link while the VM is suspended during migration. The live migration circuit buffers changes to a session state and transfers the buffered session state changes to the destination host for replay after the VM is reactivated on the destination host. The live migration circuit keeps the sessions alive during migration to alleviate connection losses.

    Network function virtualization architecture with device isolation
    18.
    发明授权
    Network function virtualization architecture with device isolation 有权

    公开(公告)号：US10445272B2

    公开(公告)日：2019-10-15

    申请号：US16027776

    申请日：2018-07-05

    Applicant: Intel Corporation

    Inventor： Kevin Devey ,  John Browne ,  Chris Macnamara ,  Eoin Walsh ,  Bruce Richardson ,  Andrew Cunningham ,  Niall Power ,  David Hunt ,  Changzheng Wei ,  Eliezer Tamir

    IPC: G06F13/38 ,  G06F1/3203 ,  G06F9/455 ,  G06F9/4401

    Abstract: A network system includes a central processing unit and a peripheral device in electrical communication with the central processing unit. The peripheral device has at least one power input and a data input. The network system also includes an out of band controller in electrical communication with the central processing unit, the peripheral device, and an external management interface. Responsive to an identified threat, the out of band controller is configured to disable the at least one power input and the data input to the peripheral device, where the disablement indicates to the central processing unit that a hot plug event has occurred with respect to the peripheral device. The out of band controller is also configured to enable auxiliary power to the peripheral device such that the out of band controller remains in communication with the peripheral device during remediation of the identified threat.

    NETWORK FUNCTION VIRTUALIZATION ARCHITECTURE WITH DEVICE ISOLATION
    19.
    发明申请
    NETWORK FUNCTION VIRTUALIZATION ARCHITECTURE WITH DEVICE ISOLATION 审中-公开

    公开(公告)号：US20190042506A1

    公开(公告)日：2019-02-07

    申请号：US16027776

    申请日：2018-07-05

    Applicant: Intel Corporation

    Inventor： Kevin Devey ,  John Browne ,  Chris Macnamara ,  Eoin Walsh ,  Bruce Richardson ,  Andrew Cunningham ,  Niall Power ,  David Hunt ,  Changzheng Wei ,  Eliezer Tamir

    IPC: G06F13/38 ,  G06F1/32 ,  G06F9/455

    Abstract: A network system includes a central processing unit and a peripheral device in electrical communication with the central processing unit. The peripheral device has at least one power input and a data input. The network system also includes an out of band controller in electrical communication with the central processing unit, the peripheral device, and an external management interface. Responsive to an identified threat, the out of band controller is configured to disable the at least one power input and the data input to the peripheral device, where the disablement indicates to the central processing unit that a hot plug event has occurred with respect to the peripheral device. The out of band controller is also configured to enable auxiliary power to the peripheral device such that the out of band controller remains in communication with the peripheral device during remediation of the identified threat.

    TECHNOLOGIES FOR DEMOTING CACHE LINES TO SHARED CACHE
    20.
    发明申请
    TECHNOLOGIES FOR DEMOTING CACHE LINES TO SHARED CACHE 审中-公开

    公开(公告)号：US20190042419A1

    公开(公告)日：2019-02-07

    申请号：US16024773

    申请日：2018-06-30

    Applicant: Intel Corporation

    Inventor： Eliezer Tamir ,  Bruce Richardson ,  Niall Power ,  Andrew Cunningham ,  David Hunt ,  Kevin Devey ,  Changzheng Wei

    IPC: G06F12/084 ,  G06F12/1072

    Abstract: Technologies for demoting cache lines to a shared cache include a compute device with at least one processor having multiple cores, a cache memory with a core-local cache and a shared cache, and a cache line demote device. A processor core of a processor of the compute device is configured to retrieve at least a portion of data of a received network packet and move the data into one or more core-local cache lines of the core-local cache. The processor core is further configured to perform a processing operation on the data and transmit a cache line demotion command to the cache line demote device subsequent to having completed the processing operation. The cache line demote device is configured to perform a cache line demotion operation to demote the data from the core-local cache lines to shared cache lines of the shared cache. Other embodiments are described herein.

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