公开(公告)号：US20160085293A1

公开(公告)日：2016-03-24

申请号：US14960693

申请日：2015-12-07

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Scott P. Bobholz ,  Raghunandan Makaram ,  Vivek Garg

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，多核处理器包括可独立执行指令的核心，每个指令以独立的电压和频率进行。 处理器可以包括具有用于提供处理器的电源管理特征的可配置性的逻辑的功率控制器。 一种这样的特征使得至少一个核可以基于存在于控制寄存器中的单个功率域指示符的状态在独立的性能状态下操作。 描述和要求保护其他实施例。

公开(公告)号：US20160026231A1

公开(公告)日：2016-01-28

申请号：US14340802

申请日：2014-07-25

Applicant: Intel Corporation

Inventor： James S. Ignowski ,  Matthew M. Bace ,  Eric J. Dehaemer ,  Chris Poirier

IPC: G06F1/32 ,  G06F1/28

CPC classification number: G06F1/206 ,  G06F1/26 ,  G06F1/28 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/5094 ,  G06F11/0754 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

Abstract: In an embodiment, a processor comprises: a plurality of cores each to execute instructions; a plurality of thermal sensors, at least one of which is associated with each of the cores; and a power control unit (PCU) coupled to the cores. The PCU includes a thermal control logic to preemptively throttle a first core by a first throttle amount when a temperature of a second core exceeds at least one thermal threshold. Note that this first core may be preemptively throttled independently of a throttling of the second core and may have a temperature of the first core does not exceed any thermal threshold. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括：多个核心，每个核心执行指令; 多个热传感器，其中至少一个与每个芯相关联; 以及耦合到所述芯的功率控制单元（PCU）。 PCU包括热控制逻辑，当第二核心的温度超过至少一个热阈值时，预先将第一核心节流第一节流量。 注意，该第一核心可以独立于第二核心的节流被预先节流，并且可以具有第一核心的温度不超过任何热阈值。 描述和要求保护其他实施例。

公开(公告)号：US10725919B2

公开(公告)日：2020-07-28

申请号：US15947829

申请日：2018-04-08

Applicant: Intel Corporation

Inventor： Herbert H. Hum ,  Brinda Ganesh ,  James R. Vash ,  Ganesh Kumar ,  Leena K. Puthiyedath ,  Scott J. Erlanger ,  Eric J. Dehaemer ,  Adrian C. Moga ,  Michelle M. Sebot ,  Richard L. Carlson ,  David Bubien ,  Eric Delano

IPC: G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

公开(公告)号：US10705960B2

公开(公告)日：2020-07-07

申请号：US15947830

申请日：2018-04-08

Applicant: Intel Corporation

Inventor： Herbert H. Hum ,  Brinda Ganesh ,  James R. Vash ,  Ganesh Kumar ,  Leena K. Puthiyedath ,  Scott J. Erlanger ,  Eric J. Dehaemer ,  Adrian C. Moga ,  Michelle M. Sebot ,  Richard L. Carlson ,  David Bubien ,  Eric DeLano

IPC: G06F12/00 ,  G06F12/0831 ,  G06F12/0811 ,  G06F12/084

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

公开(公告)号：US20190317585A1

公开(公告)日：2019-10-17

申请号：US16454378

申请日：2019-06-27

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Scott P. Bobholz ,  Raghunandan Makaram ,  Vivek Garg

IPC: G06F1/324 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/3296 ,  G06F1/26 ,  G06F1/3206

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

公开(公告)号：US20190171274A1

公开(公告)日：2019-06-06

申请号：US16271191

申请日：2019-02-08

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Scott P. Bobholz ,  Raghunandan Makaram ,  Vivek Garg

IPC: G06F1/324 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/3296 ,  G06F1/26 ,  G06F1/3206

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

公开(公告)号：US10191532B2

公开(公告)日：2019-01-29

申请号：US15048055

申请日：2016-02-19

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Scott P. Bobholz ,  Raghunandan Makaram ,  Vivek Garg

IPC: G06F1/32 ,  G06F1/26

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

公开(公告)号：US09910470B2

公开(公告)日：2018-03-06

申请号：US14970747

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Vivek Garg ,  Alexander Gendler ,  Arvind Raman ,  Ashish V. Choubal ,  Krishnakanth V. Sistla ,  Dean Mulla ,  Eric J. Dehaemer ,  Rahul Agrawal ,  Guy G. Sotomayor

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/3243 ,  Y02D10/152

Abstract: In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first telemetry data packet to a power controller according to a stagger schedule to prevent data collisions, and a global alignment counter to count a stagger alignment period. Other embodiments are described and claimed.

公开(公告)号：US09417681B2

公开(公告)日：2016-08-16

申请号：US14697541

申请日：2015-04-27

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Martin T. Rowland ,  Chris Poirier ,  Eric J. Dehaemer ,  Avinash N. Ananthakrishnan ,  Jeremy J. Shrall ,  Xiuting C. Man ,  Stephen H. Gunther ,  Krishna K. Rangan ,  Devadatta V. Bodas ,  Don Soltis ,  Hang T. Nguyen ,  Cyprian W. Woo ,  Thi Dang

IPC: G06F15/177 ,  G06F1/32 ,  G06F1/00 ,  G06F1/20

CPC classification number: G06F1/3243 ,  G06F1/206 ,  G06F1/28 ,  G06F1/3206 ,  Y02D10/152

Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.

Abstract translation: 装置的一个实施例包括具有处理器和裸片上非易失性存储资源的半导体芯片。 片上非易失性存储器可以为处理器的相同性能状态的不同配置和处理器的使用情况存储不同的适当的性能相关信息。

公开(公告)号：US20160170478A1

公开(公告)日：2016-06-16

申请号：US15048055

申请日：2016-02-19

Applicant: Intel Corporation

Inventor： Malini K. Bhandaru ,  Eric J. Dehaemer ,  Scott P. Bobholz ,  Raghunandan Makaram ,  Vivek Garg

IPC: G06F1/32

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3225 ,  G06F1/3234 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.