公开(公告)号：US20200020850A1

公开(公告)日：2020-01-16

申请号：US16474575

申请日：2017-03-23

Applicant: Intel Corporation

Inventor： Richard Dorrance ,  Farhana Sheikh

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  H04L5/14

Abstract: A spintronic device includes a first ferromagnetic layer. The first ferromagnetic layer includes a first direction of magnetic polarization. Furthermore, the spintronic device includes a second ferromagnetic layer. The second ferromagnetic layer includes a second direction of magnetic polarization opposite to the first direction. Furthermore, the spintronic device includes a long spin lifetime layer. Furthermore, the spintronic device includes a first tunnel barrier layer disposed between the first ferromagnetic layer and the long spin lifetime layer. Furthermore, the spintronic device includes a second tunnel barrier layer disposed between the second ferromagnetic layer and the long spin lifetime layer.

公开(公告)号：US20170085252A1

公开(公告)日：2017-03-23

申请号：US14861421

申请日：2015-09-22

Applicant: Intel Corporation

Inventor： Farhana Sheikh ,  Ching-En Lee ,  Feng Xue ,  Anuja S. Vaidya ,  Eduardo X. Alban ,  Albert Oskar Filip Andersson ,  Chia-Hsiang Chen ,  Shu-Ping Yeh

IPC: H03H21/00 ,  G06F17/16

CPC classification number: H03H21/0012 ,  G06F9/3877 ,  G06F17/16 ,  H03H2021/0049 ,  H03H2021/0094 ,  H03H2218/06 ,  H04B1/525

Abstract: An adaptation hardware accelerator comprises a calculation unit configured to receive a plurality of inputs at one or more predefined time intervals, wherein each time interval corresponds to a calculation iteration, the plurality of inputs being associated with a plurality of adaptive filters each having a plurality of taps, and determine a correlation data and a cross-correlation data based thereon for a given calculation iteration. The correlation data comprises a correlation matrix comprising a plurality of sub-matrices, wherein determining the correlation matrix comprises determining only the submatrices in an upper triangular portion and a diagonal portion of the correlation matrix. Further, the adaptation hardware accelerator comprises an adaptation core unit configured to determine a plurality of adaptive weights associated with the plurality of adaptive filters, respectively, based on an optimized RLS based adaptive algorithm, by utilizing the correlation data and the cross correlation data. In addition, the hardware accelerator unit comprises a convergence detector unit configured to determine a convergence parameter; and a controller configured to generate an iteration signal for each of the predefined time intervals based on the convergence parameter. The iteration signal communicates to the calculation unit and the adaptation core unit to continue with a next calculation iteration or to conclude, wherein the conclusion indicates a determination of a final value of the plurality of the adaptive weights by the adaptation core unit.

公开(公告)号：US09225521B2

公开(公告)日：2015-12-29

申请号：US14507427

申请日：2014-10-06

Applicant: Intel Corporation

Inventor： Farhana Sheikh ,  Jesse Walker ,  Sanu K. Mathew ,  Ram K. Krishnamurthy

IPC: H04L9/00 ,  H04L9/08 ,  H04L9/06 ,  H04N1/32

CPC classification number: H04L9/0861 ,  H04L9/0618 ,  H04L9/0625 ,  H04L9/0631 ,  H04L9/0637 ,  H04L9/0643 ,  H04L9/0816 ,  H04L2209/125 ,  H04L2209/24 ,  H04N1/32277

Abstract: Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data.

Abstract translation: 这里描述了用于Skein散列的装置和方法。 该装置包括可以用于接收输入数据并通过应用唯一块迭代（UBI）模式来产生散列输出数据的块密码，所述块密码包括由寄存器流水线化的至少两个混合和置换逻辑单元; 以及耦合到所述块密码的计数器，以确定所述UBI模式的序列，并且使所述块密码同时处理至少两个输入数据以产生所述散列输出数据。

公开(公告)号：US11983530B2

公开(公告)日：2024-05-14

申请号：US16833164

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Sumeet Singh Nagi ,  Farhana Sheikh ,  Scott Jeremy Weber ,  Uneeb Yaqub Rathore

IPC: G06F9/30 ,  G06F7/48 ,  G06F7/49 ,  G06F7/50 ,  G06F7/523 ,  G06F9/50 ,  G06F17/16

CPC classification number: G06F9/3001 ,  G06F7/4806 ,  G06F7/49 ,  G06F7/50 ,  G06F7/523 ,  G06F9/5027 ,  G06F17/16

Abstract: Systems and methods described herein may relate to providing a dynamically configurable circuitry able to process data associated with a variety of matrix dimensions using one or more complex number operations, one or more real number operations, or both. Configurations may be applied to the configurable circuitry to program the configurable circuitry for a next operation. The configurable circuitry may process data according to a variety of operations based at least in part on operation of a repeated processing element coupled in a compute network of processing elements.

公开(公告)号：US11205749B2

公开(公告)日：2021-12-21

申请号：US16474575

申请日：2017-03-23

Applicant: Intel Corporation

Inventor： Richard Dorrance ,  Farhana Sheikh

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H04L5/14 ,  H01L43/10

Abstract: A spintronic device includes a first ferromagnetic layer. The first ferromagnetic layer includes a first direction of magnetic polarization. Furthermore, the spintronic device includes a second ferromagnetic layer. The second ferromagnetic layer includes a second direction of magnetic polarization opposite to the first direction. Furthermore, the spintronic device includes a long spin lifetime layer. Furthermore, the spintronic device includes a first tunnel barrier layer disposed between the first ferromagnetic layer and the long spin lifetime layer. Furthermore, the spintronic device includes a second tunnel barrier layer disposed between the second ferromagnetic layer and the long spin lifetime layer.

公开(公告)号：US10673461B2

公开(公告)日：2020-06-02

申请号：US15778239

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Chia-Hsiang Chen ,  Wei Tang ,  Farhana Sheikh

IPC: H03M13/00 ,  H03M13/11 ,  H04L1/18

Abstract: A pipeline decoding system for performing pipelined decoding of a codeword characterized by one or more parity checks may include a first pipeline stage circuit configured to process a first parity set composed of one or more first parity checks of the codeword and to process a second parity set composed of one or more second parity checks of the codeword, a second pipeline stage circuit configured to generate one or more codeword update messages for the second parity set based on a first estimate of the codeword, and a third pipeline stage circuit configured to update the first estimate of the codeword with one or more codeword update messages for the first parity set to obtain a second estimate of the codeword.

公开(公告)号：US20180262224A1

公开(公告)日：2018-09-13

申请号：US15836410

申请日：2017-12-08

Applicant: Intel Corporation

Inventor： Hossein Alavi ,  Farhana Sheikh ,  Markus Dominik Mueck ,  Vladimir Ivanov

IPC: H04B1/3827 ,  H04B15/02 ,  H04B17/10 ,  H04W52/50 ,  H04W52/44

CPC classification number: H04B1/3838 ,  H04B15/02 ,  H04B17/102 ,  H04W52/44 ,  H04W52/50

Abstract: The disclosure generally relates to a method, apparatus and system for identifying non-compliant radio emissions and for enforcing compliance. In one embodiment, the disclosure relates to a dynamic radiation control of a radio by measuring a signal attribute for an outbound signal having a protocol; comparing the signal attribute with a predefined mask, the predefined mask governed by at least one of a radio location or a signal protocol; and determining whether to transmit the outbound signal.

公开(公告)号：US09967820B2

公开(公告)日：2018-05-08

申请号：US15196070

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Richard Dorrance ,  Minyoung Park ,  Alexander W. Min ,  Farhana Sheikh

IPC: H04W72/04 ,  H04W52/02 ,  H04L29/06

CPC classification number: H04W52/0229 ,  H04L1/00 ,  H04L1/0061 ,  H04L12/12 ,  H04L27/06 ,  H04L69/22 ,  Y02D70/00

Abstract: According to the present disclosure, a communication device configured to power on a main receiver to receive data from a network includes: a low power receiver configured to receive a wake up packet, including a preamble, from the network and oversample the wake up packet; a circuit arrangement including: a correlator configured to correlate the oversampled portion of the preamble; a delay and adder configured to take an output of the correlator, delay the output of the correlator, and add the output of the correlator back onto itself to produce a delay output; a peak detector configured to detect a peak pattern in the delay output; a demodulator configured to calculate a decoding threshold value to produce a demodulated data; and a packet parser configured to check the demodulated data for a data set in order to selectively output a nonzero signal to power on the main receiver.

公开(公告)号：US09935615B2

公开(公告)日：2018-04-03

申请号：US14861421

申请日：2015-09-22

Applicant: Intel Corporation

Inventor： Farhana Sheikh ,  Ching-En Lee ,  Feng Xue ,  Anuja S. Vaidya ,  Eduardo X. Alban ,  Albert Oskar Filip Andersson ,  Chia-Hsiang Chen ,  Shu-Ping Yeh

IPC: G06F17/10 ,  H03H21/00 ,  G06F17/16 ,  G06F9/38 ,  H04B1/525

CPC classification number: H03H21/0012 ,  G06F9/3877 ,  G06F17/16 ,  H03H2021/0049 ,  H03H2021/0094 ,  H03H2218/06 ,  H04B1/525

Abstract: An adaptation hardware accelerator comprises a calculation unit to receive inputs at predefined time interval(s) that correspond to a calculation iteration, the inputs associated with adaptive filters having taps, and determine correlation and cross-correlation data based thereon for a given iteration. The correlation data comprises a correlation matrix. Determining the matrix comprises determining submatrices in an upper triangular portion and a diagonal portion of the matrix. The accelerator comprises an adaptation core unit to determine adaptive weights associated with the adaptive filters, respectively, based on an adaptive algorithm, utilizing the correlation and cross correlation data. The accelerator unit comprises a convergence detector unit to determine a convergence parameter; and a controller to generate an iteration signal for each time interval based on the parameter. The iteration signal communicates to continue or conclude; the conclusion indicates determination of a final value of adaptive weights by the core unit.

公开(公告)号：US20160380653A1

公开(公告)日：2016-12-29

申请号：US14749766

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Farhana Sheikh ,  Ching-En Lee ,  Shu-Ping Yeh ,  Feng Xue ,  Anuja Surendra Vaidya

IPC: H04B1/04 ,  H04L5/14 ,  H04B1/12

CPC classification number: H04B1/0475 ,  H04B1/12 ,  H04B1/525 ,  H04L5/14

Abstract: A polynomial kernel generator is configured to mitigate nonlinearity in a receiver path from a transmitter path comprising a nonlinear component in a communication device or system. The polynomial kernel generator operates to generate polynomial kernels that can be utilized to model the nonlinearity as a function of a piecewise polynomial approximation applied to a nonlinear function of the nonlinearity. The polynomial kernel generator generates kernels in a multiplier less architecture with polynomial computations in a log domain using a fixed number of adders.

Abstract translation: 多项式核心生成器被配置为从包括通信设备或系统中的非线性分量的发射机路径减轻接收机路径中的非线性。 多项式核心发生器用于产生可用于将非线性建模为应用于非线性的非线性函数的分段多项式逼近的函数的多项式内核。 多项式内核生成器使用固定数量的加法器在日志域中使用多项式计算，在乘数少的架构中生成内核。