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    Two-level cache locking mechanism
    12.
    发明授权
    Two-level cache locking mechanism 有权
    两级缓存锁定机制

    公开(公告)号：US09558121B2

    公开(公告)日：2017-01-31

    申请号：US13729840

    申请日：2012-12-28

    Applicant: INTEL CORPORATION

    Inventor： Li-Gao Zei ,  Fernando Latorre ,  Steffen Kosinski ,  Jaroslaw Topp ,  Varun Mohandru ,  Lutz Naethke

    IPC: G06F12/00 ,  G06F12/08 ,  G06F12/10

    CPC classification number: G06F12/0846 ,  G06F12/0864 ,  G06F12/1063

    Abstract: A virtually tagged cache may be configured to index virtual address entries in the cache into lockable sets based on a page offset value. When a memory operation misses on the virtually tagged cache, only the one set of virtual address entries with the same page offset may be locked. Thereafter, this general lock may be released and only an address stored in the physical tag array matching the physical address and a virtual address in the virtual tag array corresponding to the matching address stored in the physical tag array may be locked to reduce the amount and duration of locked addresses. The machine may be stalled only if a particular memory address request hits and/or tries to access one or more entries in a locked set. Devices, systems, methods, and computer readable media are provided.

    Abstract translation: 虚拟标记的高速缓存可以被配置为基于页面偏移值将高速缓存中的虚拟地址条目索引到可锁定集合。 当内存操作错过虚拟标记的缓存时，只有一组具有相同页偏移量的虚拟地址条目可能被锁定。 此后，可以解除该通用锁定，并且仅锁定与物理地址匹配的物理标签阵列中存储的地址和与物理标签阵列中存储的匹配地址相对应的虚拟标签阵列中的虚拟地址，以减少数量和 锁定地址的持续时间。 只有当特定的存储器地址请求命中和/或尝试访问锁定集中的一个或多个条目时，才可能停止该机器。 提供了设备，系统，方法和计算机可读介质。

    Store forwarding for data caches
    16.
    发明授权
    Store forwarding for data caches 有权
    存储转发数据缓存

    公开(公告)号：US09507725B2

    公开(公告)日：2016-11-29

    申请号：US13729945

    申请日：2012-12-28

    Applicant: INTEL CORPORATION

    Inventor： Steffen Kosinski ,  Fernando Latorre ,  Niranjan Cooray ,  Stanislav Shwartsman ,  Ethan Kalifon ,  Varun Mohandru ,  Pedro Lopez ,  Tom Aviram-Rosenfeld ,  Jaroslav Topp ,  Li-Gao Zei

    IPC: G06F12/00 ,  G06F12/08

    CPC classification number: G06F12/0895 ,  G06F12/0855 ,  G06F12/0866

    Abstract: A bit or other vector may be used to identify whether an address range entered into an intermediate buffer corresponds to most recently updated data associated with the address range. A bit or other vector may also be used to identify whether an address range entered into an intermediate buffer overlaps with an address range of data that is to be loaded. A processing device may then determine whether to obtain data that is to be loaded entirely from a cache, entirely from an intermediate buffer which temporarily buffers data destined for a cache until the cache is ready to accept the data, or from both the cache and the intermediate buffer depending on the particular vector settings. Systems, devices, methods, and computer readable media are provided.

    Abstract translation: 可以使用位或其他向量来识别输入中间缓冲器的地址范围是否对应于与地址范围相关联的最近更新的数据。 还可以使用位或其他向量来识别输入中间缓冲器的地址范围是否与要加载的数据的地址范围重叠。 然后，处理设备可以完全从中间缓冲区获得要从缓存中完全加载的数据，该中间缓冲器临时缓冲目的地为高速缓存的数据，直到高速缓存准备好接受数据，或者从高速缓存和 中间缓冲区取决于特定的向量设置。 提供了系统，设备，方法和计算机可读介质。

    Instruction and Logic for Support of Code Modification In Translation Lookaside Buffers
    19.
    发明申请
    Instruction and Logic for Support of Code Modification In Translation Lookaside Buffers 有权
    在翻译后备缓冲区中支持代码修改的指令和逻辑

    公开(公告)号：US20160292081A1

    公开(公告)日：2016-10-06

    申请号：US15178008

    申请日：2016-06-09

    Applicant: Intel Corporation

    Inventor： Jaroslaw Topp ,  Niranjan L. Cooray ,  Fernando Latorre

    IPC: G06F12/10 ,  G06F9/30

    CPC classification number: G06F12/1027 ,  G06F9/30003 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/3877 ,  G06F9/3887 ,  G06F12/0815 ,  G06F12/0888 ,  G06F12/1081 ,  G06F2212/1016 ,  G06F2212/30 ,  G06F2212/302 ,  G06F2212/50 ,  G06F2212/68

    Abstract: A processor includes a core with logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor further includes a translation lookaside buffer including logic to store translation indicators from a physical map. Each translation indicator indicates whether a corresponding memory location includes translated code to be protected. The processor further includes a translation indicator agent including logic to determine whether the buffer indicates whether the memory location has been modified subsequent to translation of the instruction.

    Abstract translation: 处理器包括具有执行翻译指令的逻辑的核心。 转换后的指令从存储在存储单元中的指令转换。 处理器还包括翻译后备缓冲器，其包括用于存储来自物理图的转换指示符的逻辑。 每个翻译指示符指示对应的存储器位置是否包括要保护的翻译代码。 处理器还包括翻译指示剂代理，其包括用于确定缓冲器是否指示在指令的翻译之后是否已经修改了存储器位置的逻辑。

    Adaptive data prefetching
    20.
    发明授权
    Adaptive data prefetching 有权
    自适应数据预取

    公开(公告)号：US09280474B2

    公开(公告)日：2016-03-08

    申请号：US13976325

    申请日：2013-01-03

    Applicant: Intel Corporation

    Inventor： Demos Pavlou ,  Pedro Lopez ,  Mirem Hyuseinova ,  Fernando Latorre ,  Steffen Kosinski ,  Ralf Goettsche ,  Varun K. Mohandru

    IPC: G06F12/08 ,  G06F12/02 ,  G06F9/06 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38

    CPC classification number: G06F12/0862 ,  G06F9/06 ,  G06F9/30 ,  G06F9/3455 ,  G06F9/383 ,  G06F12/02 ,  G06F2212/6026

    Abstract: A system and method for adaptive data prefetching in a processor enables adaptive modification of parameters associated with a prefetch operation. A stride pattern in successive addresses of a memory operation may be detected, including determining a stride length (L). Prefetching of memory operations may be based on a prefetch address determined from a base memory address, the stride length L, and a prefetch distance (D). A number of prefetch misses may be counted at a miss prefetch count (C). Based on the value of the miss prefetch count C, the prefetch distance D may be modified. As a result of adaptive modification of the prefetch distance D, an improved rate of cache hits may be realized.

    Abstract translation: 用于处理器中自适应数据预取的系统和方法使得能够对与预取操作相关联的参数进行自适应修改。 可以检测存储器操作的连续地址中的步幅图案，包括确定步幅长度（L）。 存储器操作的预取可以基于从基本存储器地址确定的预取地址，步幅长度L和预取距离（D）。 可以以错误预取计数（C）计数多个预取缺失。 基于缺省预取计数C的值，可以修改预取距离D. 作为预取距离D的自适应修改的结果，可以实现改进的高速缓存命中率。

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