公开(公告)号：US20190171515A1

公开(公告)日：2019-06-06

申请号：US15831195

申请日：2017-12-04

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Stanislav Shwartsman ,  Jared W. Stark, IV ,  Lihu Rappoport ,  Igor Yanover ,  George Leifman

IPC: G06F11/07 ,  G06F12/02 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F11/0793 ,  G06F9/30043 ,  G06F9/30058 ,  G06F9/3802 ,  G06F9/3855 ,  G06F11/0721 ,  G06F12/0215 ,  G06F12/0253 ,  G06F2212/654 ,  G06F2212/702

Abstract: A method for handling load faults in an out-of-order processor is described. The method includes detecting, by a memory ordering buffer of the out-of-order processor, a load fault corresponding to a load instruction that was executed out-of-order by the out-of-order processor; determining, by the memory ordering buffer, whether instant reclamation is available for resolving the load fault of the load instruction; and performing, in response to determining that instant reclamation is available for resolving the load fault of the load instruction, instant reclamation to re-fetch the load instruction for execution prior to attempting to retire the load instruction.

公开(公告)号：US10303605B2

公开(公告)日：2019-05-28

申请号：US15214895

申请日：2016-07-20

Applicant: INTEL CORPORATION

Inventor： Raanan Sade ,  Joseph Nuzman ,  Stanislav Shwartsman ,  Igor Yanover ,  Liron Zur

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/0815 ,  G06F12/0893

Abstract: An example system on a chip (SoC) includes a processor, a cache, and a main memory. The SoC can include a first memory to store data in a memory line, wherein the memory line is set to an invalid state. The processor can include a processor coupled to the first memory. The processor can determine that a data size of a first data set received from an application is within a data size range. The processor can determine that an aggregate data size of the first data set and a second data set received from the application is at least a same data size as data size of the memory line. The processor can perform an invalid-to-modify (I2M) operation to change the memory line from the invalid state to a modified state. The processor can write the first data set and the second data set to the memory line.

公开(公告)号：US20180210842A1

公开(公告)日：2018-07-26

申请号：US15416549

申请日：2017-01-26

Applicant: Intel Corporation

Inventor： Joseph Nuzman ,  Raanan Sade ,  Igor Yanover ,  Ron Gabor ,  Amit Gradstein

IPC: G06F12/1036

CPC classification number: G06F12/1036 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/657 ,  G06F2212/683 ,  G06F2212/684

Abstract: A processing device including a linear address transformation circuit to determine that a metadata value stored in a portion of a linear address falls within a pre-defined metadata range. The metadata value corresponds to a plurality of metadata bits. The linear address transformation circuit to replace each of the plurality of the metadata bits with a constant value.

公开(公告)号：US20160103785A1

公开(公告)日：2016-04-14

申请号：US14881111

申请日：2015-10-12

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Robert Valentine ,  Guy Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

IPC: G06F15/80 ,  G06F9/30

CPC classification number: G06F15/8007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3887

Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

公开(公告)号：US12182571B2

公开(公告)日：2024-12-31

申请号：US18100194

申请日：2023-01-23

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Menachem Adelman ,  Milind B. Girkar ,  Zeev Sperber ,  Mark J. Charney ,  Bret L. Toll ,  Rinat Rappoport ,  Jesus Corbal ,  Stanislav Shwartsman ,  Dan Baum ,  Igor Yanover ,  Alexander F. Heinecke ,  Barukh Ziv ,  Elmoustapha Ould-Ahmed-Vall ,  Yuri Gebil ,  Raanan Sade

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/38 ,  G06F17/16

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.

公开(公告)号：US12106100B2

公开(公告)日：2024-10-01

申请号：US16487421

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Mark J. Charney ,  Elmoustapha Ould-Ahmed-Vall ,  Dan Baum ,  Zeev Sperber ,  Jesus Corbal ,  Bret L. Toll ,  Raanan Sade ,  Igor Yanover ,  Yuri Gebil ,  Rinat Rappoport ,  Stanislav Shwartsman ,  Menachem Adelman ,  Simon Rubanovich

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/38 ,  G06F17/16

CPC classification number: G06F9/30036 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/762 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/3818 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

Abstract: Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.

公开(公告)号：US12099597B2

公开(公告)日：2024-09-24

申请号：US18384996

申请日：2023-10-30

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Sagi Meller ,  Gavri Berger ,  Igor Yanover

IPC: G06F21/00 ,  G06F1/32 ,  G06F9/38 ,  G06F21/54 ,  G06F21/56

CPC classification number: G06F21/54 ,  G06F1/32 ,  G06F9/3802 ,  G06F21/561 ,  G06F2221/034

Abstract: An apparatus and method for intelligent power virus protection in a processor. For example, one embodiment of a processor comprises: first circuitry including an instruction fetch circuit to fetch instructions, each instruction comprising an instruction type and an associated width comprising a number of bits associated with source and/or destination operand values associated with the instruction; detection circuitry to detect one or more instructions of a particular type and/or width; evaluation circuitry to evaluate an impact of power virus protection (PVP) circuitry when executing the one or more instructions based on the detected instruction types and/or widths; and control circuitry, based on the evaluation, to configure the PVP circuitry in accordance with the evaluation performed by the evaluation circuitry.

公开(公告)号：US11580031B2

公开(公告)日：2023-02-14

申请号：US16813346

申请日：2020-03-09

Applicant: INTEL CORPORATION

Inventor： Stanislav Shwartsman ,  Igor Yanover ,  Assaf Zaltsman ,  Ron Rais

IPC: G06F12/1027 ,  G06F9/30

Abstract: Systems, methods, and apparatuses relating to hardware for split data translation lookaside buffers. In one embodiment, a processor includes a decode circuit to decode instructions into decoded instructions, an execution circuit to execute the decoded instructions, and a memory circuit comprising a load data translation lookaside buffer circuit and a store data translation lookaside buffer circuit separate and distinct from the load data translation lookaside buffer circuit, wherein the memory circuit sends a memory access request of the instructions to the load data translation lookaside buffer circuit when the memory access request is a load data request and to the store data translation lookaside buffer circuit when the memory access request is a store data request to determine a physical address for a virtual address of the memory access request.

公开(公告)号：US11567765B2

公开(公告)日：2023-01-31

申请号：US16487766

申请日：2017-07-01

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Menachem Adelman ,  Milind B. Girkar ,  Zeev Sperber ,  Mark J. Charney ,  Bret L. Toll ,  Rinat Rappoport ,  Jesus Corbal ,  Stanislav Shwartsman ,  Dan Baum ,  Igor Yanover ,  Alexander F. Heinecke ,  Barukh Ziv ,  Elmoustapha Ould-Ahmed-Vall ,  Yuri Gebil

IPC: G06F9/38 ,  G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F17/16 ,  G06F7/76

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in the form of decode circuitry to decode an instruction having fields for an opcode, a destination matrix operand identifier, and source memory information, and execution circuitry to execute the decoded instruction to load groups of strided data elements from memory into configured rows of the identified destination matrix operand to memory.

公开(公告)号：US10936041B2

公开(公告)日：2021-03-02

申请号：US16369793

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Igor Yanover ,  Gavri Berger ,  Edo Hachamo ,  Elkana Korem ,  Hanan Shomroni ,  Daniela Kaufman ,  Lev Makovsky ,  Haim Granot

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3206

Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.