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    Compression format for high bandwidth dictionary compression
    13.
    发明授权
    Compression format for high bandwidth dictionary compression 有权
    高带宽字典压缩的压缩格式

    公开(公告)号：US09306598B2

    公开(公告)日：2016-04-05

    申请号：US14193427

    申请日：2014-02-28

    Applicant: Intel Corporation

    Inventor： Ilan Pardo ,  Ido Y. Soffair ,  Dror Reif ,  Debendra Das Sharma ,  Akshay G. Pethe

    IPC: H03M7/00 ,  H03M7/30

    CPC classification number: H03M7/6023 ,  H03M7/3088

    Abstract: Method, apparatus, and systems employing dictionary-based high-bandwidth lossless compression. A pair of dictionaries having entries that are synchronized and encoded to support compression and decompression operations are implemented via logic at a compressor and decompressor. The compressor/decompressor logic operatives in a cooperative manner, including implementing the same dictionary update schemes, resulting in the data in the respective dictionaries being synchronized. The dictionaries are also configured with replaceable entries, and replacement policies are implemented based on matching bytes of data within sets of data being transferred over the link. Various schemes are disclosed for entry replacement, as well as a delayed dictionary update technique. The techniques support line-speed compression and decompression using parallel operations resulting in substantially no latency overhead.

    Abstract translation: 使用基于字典的高带宽无损压缩的方法，装置和系统。 具有同步和编码以支持压缩和解压缩操作的条目的一对字典通过压缩器和解压缩器的逻辑来实现。 压缩器/解压缩器逻辑操作以协作的方式，包括实现相同的字典更新方案，导致相应词典中的数据被同步。 字典还配置有可替换条目，并且替换策略基于通过链接传送的数据集合中的数据的匹配字节来实现。 公开了用于条目替换的各种方案以及延迟字典更新技术。 该技术支持使用并行操作的线速压缩和解压缩，从而实质上无延迟开销。

    Apparatus and method for retrieving elements from a linked structure
    16.
    发明授权
    Apparatus and method for retrieving elements from a linked structure 有权

    公开(公告)号：US10095517B2

    公开(公告)日：2018-10-09

    申请号：US14979236

    申请日：2015-12-22

    Applicant: Intel Corporation

    Inventor： Oren Ben-Kiki ,  Ilan Pardo

    IPC: G06F9/30 ,  G06F9/34 ,  G06F9/345

    Abstract: An apparatus and method are described for retrieving elements from a linked structure. For example, one embodiment of an apparatus comprises: a decode unit to decode a first instruction, the first instruction to utilize a current address value, an end address value, and an offset; and an execution unit to execute the first instruction to cause the execution unit to compare the current address value with the end address value, the execution unit to perform no additional operation with respect to the first instruction if the current address value is equal to the end address value; and if the current address value is not equal to the end address value, then the execution unit to add the offset value to the current address value to identify a next address pointer within an element structure, the execution unit to further set the current address value equal to the next address pointer.

    Apparatus and method for low-latency invocation of accelerators
    17.
    发明授权
    Apparatus and method for low-latency invocation of accelerators 有权

    公开(公告)号：US10089113B2

    公开(公告)日：2018-10-02

    申请号：US15282082

    申请日：2016-09-30

    Applicant: Intel Corporation

    Inventor： Oren Ben-Kiki ,  Ilan Pardo ,  Robert Valentine ,  Eliezer Weissmann ,  Dror Markovich ,  Yuval Yosef

    IPC: G06F9/38 ,  G06F9/30 ,  G06F11/07 ,  G06F9/54 ,  G06F12/0875

    Abstract: An apparatus and method are described for providing low-latency invocation of accelerators. For example, a system according to one embodiment comprises: a processor includes a plurality of simultaneous multithreading (SMT) cores, at least one shared cache circuit to be shared among two or more of the SMT cores; and at least one of the SMT cores including at least one level 2 (L2) cache circuit to store both instructions and data and communicatively coupled to the instruction cache circuit and the data cache circuit, a communication interconnect circuit including a peripheral component interconnect express (PCIe) circuit to communicatively couple one or more of the SMT cores to an accelerator device and a memory access circuit to identify an accelerator context save/restore region in a memory responsive to a context save/restore value, the accelerator context save/restore region to share an accelerator context state.

    Apparatus to reduce idle link power in a platform
    18.
    发明授权
    Apparatus to reduce idle link power in a platform 有权
    降低平台空闲链路功率的装置

    公开(公告)号：US09367116B2

    公开(公告)日：2016-06-14

    申请号：US14978340

    申请日：2015-12-22

    Applicant: Intel Corporation

    Inventor： Paul S. Diefenbaugh ,  Robert E. Gough ,  Yuval Bachrach ,  Mikal C. Hunsaker ,  Rafi Ben-Tal ,  Ilan Pardo ,  Gideon Prat ,  David J. Harriman

    IPC: G06F1/26 ,  G06F1/32

    CPC classification number: G06F1/325 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3278 ,  G06F1/3287 ,  Y02D10/157 ,  Y02D10/171

    Abstract: A system on a chip (SoC) is provided including processing cores and a root complex. The transaction requests are communicated between a root port of the root complex and a device, the root port including electrical idle (EI) exit detect circuitry and a reference clock source. The root port supports a first link state, in which the reference clock source and EI exit detect circuitry of the root port are disabled but a common mode voltage is maintained, and a second link state, in which the reference clock source and EI exit detect circuitry are disabled and the common mode voltage is not maintained. The root port transitions to the first link state based on a service latency requirement of the device being less than a threshold and to the second link state based on the service latency requirement being greater than or equal to the threshold.

    Abstract translation: 提供了一种芯片系统（SoC），包括处理核心和根系统。 事务请求在根组合的根端口和设备之间传送，根端口包括电空闲（EI）出口检测电路和参考时钟源。 根端口支持第一链路状态，其中根端口的参考时钟源和EI出口检测电路被禁用，但保持共模电压，第二链路状态，其中参考时钟源和EI退出检测 电路被禁用，并且不保持共模电压。 根据服务等待时间要求小于阈值，根据服务等待时间要求大于或等于阈值，根端口转换到第一链路状态。

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