公开(公告)号：US20210082154A1

公开(公告)日：2021-03-18

申请号：US17003040

申请日：2020-08-26

Applicant: INTEL CORPORATION

Inventor： Carson BROWNLEE ,  Carsten BENTHIN ,  Joshua BARCZAK ,  Kai XIAO ,  Michael APODACA ,  Prasoonkumar SURTI ,  Thomas RAOUX

IPC: G06T9/40 ,  G06T15/06 ,  G06T15/20 ,  G06T1/60

Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.

公开(公告)号：US20210042987A1

公开(公告)日：2021-02-11

申请号：US17079191

申请日：2020-10-23

Applicant: INTEL CORPORATION

Inventor： Karthik VAIDYANATHAN ,  Michael APODACA ,  Thomas RAOUX ,  Carsten BENTHIN ,  Kai XIAO ,  Carson BROWNLEE ,  Joshua BARCZAK

IPC: G06T15/06 ,  G06T1/60 ,  G06T9/00 ,  G06T5/00

Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.

公开(公告)号：US20170163286A1

公开(公告)日：2017-06-08

申请号：US15039544

申请日：2013-12-26

Applicant: Intel Corporation

Inventor： Zuoguo WU ,  Debendra DAS SHARMA ,  Md. Mohiuddin MAZUMDER ,  Subas BASTOLA ,  Kai XIAO

IPC: H03M13/11 ,  G06F13/42 ,  G06F13/40 ,  G06F13/36

CPC classification number: H03M13/11 ,  G06F13/36 ,  G06F13/385 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2213/0026

Abstract: An identification is made that a link is to exit an active state, the link comprising a plurality of lanes. Parity information is maintained for the lanes based on data previously sent over the link, and an indication of the parity information is sent prior to the exit from the active state.

公开(公告)号：US20240186206A1

公开(公告)日：2024-06-06

申请号：US18438450

申请日：2024-02-10

Applicant: Intel Corporation

Inventor： Satish PRATHABAN ,  Ramaswamy PARTHASARATHY ,  Biswajit PATRA ,  Tongyan ZHAI ,  Jeff KU ,  Min Suet LIM ,  Yi HUANG ,  Kai XIAO ,  Gene F. YOUNG ,  Weimin SHI

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/427 ,  H01L25/065 ,  H01L25/18 ,  H05K1/02

CPC classification number: H01L23/367 ,  H01L23/427 ,  H01L25/0655 ,  H01L25/18 ,  H05K1/0203 ,  H05K1/0262 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/1427 ,  H01L2924/15311

Abstract: Systems, apparatuses and methods may provide for technology that includes a voltage regulator, a board assembly including a die and a circuit board electrically coupled to a first side of the die, and a thermal dissipation assembly thermally and electrically coupled to a second side of the die, wherein the thermal dissipation assembly is further electrically coupled to the voltage regulator. In one example, the thermal dissipation assembly includes a vapor chamber and the technology further includes a plurality of copper plates electrically coupled to the voltage regulator and a package substrate containing the die, wherein the plurality of copper plates are further thermally coupled to the vapor chamber.

公开(公告)号：US20230137438A1

公开(公告)日：2023-05-04

申请号：US18090810

申请日：2022-12-29

Applicant: INTEL CORPORATION

Inventor： Karthik VAIDYANATHAN ,  Michael APODACA ,  Thomas RAOUX ,  Carsten BENTHIN ,  Kai XIAO ,  Carson BROWNLEE ,  Joshua BARCZAK

IPC: G06T15/06 ,  G06T1/60

Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.

公开(公告)号：US20210012553A1

公开(公告)日：2021-01-14

申请号：US17032964

申请日：2020-09-25

Applicant: INTEL CORPORATION

Inventor： Michael APODACA ,  Carsten BENTHIN ,  Kai XIAO ,  Carson BROWNLEE ,  Timothy ROWLEY ,  Joshua BARCZAK ,  Travis SCHLUESSLER

IPC: G06T15/06 ,  G06F16/901 ,  G06F7/14 ,  G06F9/38

Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.

公开(公告)号：US20190051963A1

公开(公告)日：2019-02-14

申请号：US16164352

申请日：2018-10-18

Applicant: Intel Corporation

Inventor： Jingbo LI ,  Kai XIAO ,  Howard HECK ,  Kai WANG

IPC: H01P5/02 ,  H01B7/04 ,  H01R12/73 ,  H01P3/02

Abstract: In accordance with embodiments disclosed herein, there is provided a high-density low-loss cable and connector assembly. A cable assembly includes a first cable connector, a bulk cable section, and a first cable transition section. The bulk cable section includes a first plurality of conductive wires of a first wire thickness. The first cable transition section includes a second plurality of conductive wires that has a first distal end connected to the bulk cable section and a second distal end connected to the first cable connector. Each of the second plurality of conductive wires transitions from the first wire thickness at the first distal end to a second wire thickness that is less than the first wire thickness at the second distal end. Each of the second plurality of conductive wires in the first distal end is connected to a corresponding conductive wire of the first plurality of conductive wires.