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    Concurrent compute and ECC for in-memory matrix vector operations
    11.
    发明授权
    Concurrent compute and ECC for in-memory matrix vector operations 有权

    公开(公告)号：US11513893B2

    公开(公告)日：2022-11-29

    申请号：US17128414

    申请日：2020-12-21

    Applicant: Intel Corporation

    Inventor： Somnath Paul ,  Charles Augustine ,  Chen Koren ,  George Shchupak ,  Muhammad M. Khellah

    IPC: G06F11/00 ,  G06F11/10 ,  G06N3/08

    Abstract: A system includes a compute circuit that preemptively performs a computation on a data word before receiving an indication of data errors from an error checking and correction (ECC) circuit. The ECC circuit reads the data word from a memory array and performs error detection and error correction on the data word. The compute circuit reads the data word and performs the computation on the data word to generate an output value, without waiting for the ECC circuit to check and correct the data word. In response to error detection in the data word by the ECC circuit, the compute circuit delays outputting the output value until correction of the output value in accordance with the error detection by the ECC circuit.

    CONCURRENT COMPUTE AND ECC FOR IN-MEMORY MATRIX VECTOR OPERATIONS
    12.
    发明申请
    CONCURRENT COMPUTE AND ECC FOR IN-MEMORY MATRIX VECTOR OPERATIONS 有权

    公开(公告)号：US20210109809A1

    公开(公告)日：2021-04-15

    申请号：US17128414

    申请日：2020-12-21

    Applicant: Intel Corporation

    Inventor： Somnath Paul ,  Charles Augustine ,  Chen Koren ,  George Shchupak ,  Muhammad M. Khellah

    IPC: G06F11/10 ,  G06N3/08

    Abstract: A system includes a compute circuit that preemptively performs a computation on a data word before receiving an indication of data errors from an error checking and correction (ECC) circuit. The ECC circuit reads the data word from a memory array and performs error detection and error correction on the data word. The compute circuit reads the data word and performs the computation on the data word to generate an output value, without waiting for the ECC circuit to check and correct the data word. In response to error detection in the data word by the ECC circuit, the compute circuit delays outputting the output value until correction of the output value in accordance with the error detection by the ECC circuit.

    FLIP-FLOP CIRCUIT WITH LOW-LEAKAGE TRANSISTORS
    18.
    发明申请
    FLIP-FLOP CIRCUIT WITH LOW-LEAKAGE TRANSISTORS 有权

    公开(公告)号：US20180181175A1

    公开(公告)日：2018-06-28

    申请号：US15392559

    申请日：2016-12-28

    Applicant: Intel Corporation

    Inventor： Charles Augustine ,  Rafael Rios ,  Somnath Paul ,  Muhammad M. Khellah

    IPC: G06F1/26 ,  H03K3/356 ,  H03K3/012 ,  G06F1/32

    Abstract: Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.

    Memory cell with improved write margin
    19.
    发明授权
    Memory cell with improved write margin 有权

    公开(公告)号：US09978447B2

    公开(公告)日：2018-05-22

    申请号：US15496655

    申请日：2017-04-25

    Applicant: Intel Corporation

    Inventor： Yih Wang ,  Muhammad M. Khellah ,  Fatih Hamzaoglu

    IPC: G11C11/419 ,  G11C11/413 ,  G11C11/417 ,  G11C11/412

    CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C5/148 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417

    Abstract: Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.

    Graphics processor sub-domain voltage regulation
    20.
    发明授权
    Graphics processor sub-domain voltage regulation 有权
    图形处理器子域电压调节

    公开(公告)号：US09563263B2

    公开(公告)日：2017-02-07

    申请号：US14134598

    申请日：2013-12-19

    Applicant: Intel Corporation

    Inventor： Subramaniam Maiyuran ,  Muhammad M. Khellah ,  James W. Tschanz

    IPC: G06F1/32

    CPC classification number: G06F1/3296 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172

    Abstract: Voltage regulation of processor sub-domains supplied by a same voltage domain power supply rail. Voltage to certain logic units within the voltage domain may be reduced relative to other logic units of the voltage domain, reducing idle time at high power. In an embodiment, a first voltage-regulated sub-domain includes at least one execution unit (EU) while a second voltage-regulated sub-domain includes at least one texture sampler to provide flexibility in setting the graphics core power-performance point beyond modulating active EU count through power domain (gating) control. In embodiments, a sub-domain voltage is regulated by an on-chip DLDO for fast voltage switching. Clock frequency and sub-domain voltage may be switched faster than the voltage of the voltage domain supply rail, permitting a more finely grained power management that can be responsive to EU workload demand.

    Abstract translation: 由相同的电压域电源轨提供的处理器子域的电压调节。 电压域内的某些逻辑单元的电压可以相对于电压域的其它逻辑单元减小，从而在高功率下减少空闲时间。 在一个实施例中，第一电压调节子域包括至少一个执行单元（EU），而第二电压调节子域包括至少一个纹理采样器，以提供设置图形核心功率性能点超出调制的灵活性 通过电源域（门控）控制有效的欧盟计数。 在实施例中，子域电压由用于快速电压切换的片上DLDO调节。 时钟频率和子域电压可能比电压域电源轨的电压更快，从而允许更精细的电源管理，可以响应欧盟的工作负载需求。

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