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11.发明授权公开(公告)号：US11789516B2
公开(公告)日：2023-10-17
申请号：US17440688
申请日：2020-05-22
Applicant: Intel Corporation
Inventor： Chen Ranel , Christopher J. Lake , Hem Doshi , Ido Melamed , Vijay Degalahal , Yevgeni Sabin , Reena Patel , Yoav Ben-Raphael , Nimrod Angel , Efraim Rotem , Shaun Conrad , Tomer Ziv , Nir Rosenzweig , Esfir Natanzon , Yoni Aizik , Arik Gihon , Natanel Abitan
CPC classification number: G06F1/324
Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.
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公开(公告)号：US11157329B2
公开(公告)日：2021-10-26
申请号：US16523009
申请日：2019-07-26
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Hisham Abu-Salah , Nir Rosenzweig , Efraim Rotem
Abstract: A processor comprises multiple cores and power management control logic to determine (a) a preliminary frequency for each of the cores and (b) a maximum frequency, based on the preliminary frequencies. The power management control logic is also to determines a dynamic tuning frequency, based on the maximum frequency and a reduction factor. In response to the dynamic tuning frequency for a selected core being greater than the preliminary frequency for that core, the power management control logic is to set the core to a frequency that is at least equal to the dynamic tuning frequency. In response to the preliminary frequency for the selected core being greater than the dynamic tuning frequency for that core, the power management control logic is to set the core to a frequency that is at least equal to the preliminary frequency. Other embodiments are described and claimed.
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公开(公告)号：US10372198B2
公开(公告)日：2019-08-06
申请号：US15686222
申请日：2017-08-25
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Efraim Rotem , Hisham Abu Salah , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Gal Leibovich , Yevgeni Sabin , Shay Levy
IPC: G06F1/26 , G06F1/32 , G06F1/00 , G06F1/3287 , G06F1/324 , G06F1/3234 , G06F1/3296 , G06F9/50
Abstract: In one embodiment, a processor comprises: a plurality of processing engines including a first processing engine and a second processing engine to independently execute instructions; and a power controller including a performance state control logic to control a performance state of at least one of the processing engines, and a first logic to determine an average number of active processing engines over a first window, an estimated activity level of the processor for the first window, and adjust at least one of a window length at which the performance state control logic is to perform a performance state determination and at least one activity level threshold, based at least in part on a comparison of the estimated activity level and the average number of active processing engines. Other embodiments are described and claimed.
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公开(公告)号：US10345889B2
公开(公告)日：2019-07-09
申请号：US15668762
申请日：2017-08-04
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Efraim Rotem , Barnes Cooper , Paul S. Diefenbaugh , Guy M. Therien , Michael Mishaeli , Nadav Shulman , Ido Melamed , Niv Tokman , Alexander Gendler , Arik Gihon , Yevgeni Sabin , Hisham Abu Salah , Esfir Natanzon
IPC: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F11/07
Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.
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公开(公告)号：US20180120924A1
公开(公告)日：2018-05-03
申请号：US15668762
申请日：2017-08-04
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Yoni Aizik , Doron Rajwan , Nir Rosenzweig , Efraim Rotem , Barnes Cooper , Paul S. Diefenbaugh , Guy M. Therien , Michael Mishaeli , Nadav Shulman , Ido Melamed , Niv Tokman , Alexander Gendler , Arik Gihon , Yevgeni Sabin , Hisham Abu Salah , Esfir Natanzon
CPC classification number: G06F1/3287 , G06F1/3203 , G06F1/324 , G06F11/0757 , Y02D10/126 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US09927859B2
公开(公告)日：2018-03-27
申请号：US15175741
申请日：2016-06-07
Applicant: Intel Corporation
Inventor： Nir Rosenzweig , Evgeny Bolotin , Guy Satat , Hisham Abu Salah
CPC classification number: G06F1/3203 , G06F1/26 , G06F1/324 , G06F9/38 , H03K3/0315 , H03L7/08 , Y02D10/126
Abstract: Interconnect frequency control technologies of adjusting an operating frequency of a communication interconnect between an integrated circuit comprising multiple functional hardware units are described. A power management unit (PMU) is configured to collect workload data from the functional hardware units and determine a workload metric from the workload data. The PMU adjusts an operating frequency of the communication interconnect in view of the workload metric.
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公开(公告)号：US20180004269A1
公开(公告)日：2018-01-04
申请号：US15197083
申请日：2016-06-29
Applicant: Intel Corporation
Inventor： Nir Rosenzweig , Efraim Rotem , Alexander Gendler , Ankush Varma
IPC: G06F1/32
CPC classification number: G06F1/324 , G06F1/26 , G06F1/28 , G06F1/3203 , G06F1/3206 , G06F1/3234 , G06F1/3243 , G06F1/325 , G06F1/329 , G06F1/3296 , G06F9/38 , G06F9/44 , Y02D10/126 , Y02D10/152
Abstract: A processor includes an execution engine and a power controller. The execution engine includes circuitry to determine an increased current for the execution engine. The power controller includes circuitry to determine a new dynamic capacitance for the execution engine based upon the increased current, calculate a new power consumption for the execution engine based upon the new dynamic capacitance, utilize the new power consumption to evaluate a new aggregate demand for power of a plurality of engines including the execution engine, and evaluate power provisioning of the processor based upon the new power consumption for the execution engine.
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公开(公告)号：US09612652B2
公开(公告)日：2017-04-04
申请号：US13631907
申请日：2012-09-29
Applicant: Intel Corporation
Inventor： Nir Rosenzweig , Efraim Rotem , Jawad Haj-Yihia , Ohad Falik
CPC classification number: G06F1/3296 , G06F1/3203 , G06F1/3209 , G06F1/3215 , G06F1/3287 , Y02D10/171
Abstract: Methods and apparatus relating to controlling power consumption by a power management link are described. In one embodiment, the physical interface of a power management (PM) link is shut down when a processor is in a sleep state (e.g., to conserve power), while maintaining the availability of the processor for communication to a (e.g., embedded) controller over the PM link. Other embodiments are also disclosed and claimed.
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公开(公告)号：US20170038815A1
公开(公告)日：2017-02-09
申请号：US15331051
申请日：2016-10-21
Applicant: Intel Corporation
Inventor： Efraim Rotem , Nir Rosenzweig , Doron Rajwan , Nadav Shulman , Gal Leibovich , Tomer Ziv , Amit Gabai , Jorge P. Rodriguez , Jeffrey A. Carlson
CPC classification number: G06F1/324 , G05F1/10 , G06F1/28 , G06F1/3206 , H03L7/08 , Y02D10/126
Abstract: A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an integrated circuit (IC), calculating a sum of expected powers for a plurality of domains in the IC by calculating an expected current for each of the plurality of domains based on an individual domain frequency in the new state and multiplying the expected current with its associated voltage for each of the plurality of domains for the new state; comparing the sum to a power limit; and if the sum is greater than the power limit, then reducing the individual domain frequency associated with at least one domain in the plurality of domains to maintain the total instantaneous power of the IC below the power limit.
Abstract translation: 一种用于提供主动电流保护的方法和装置。 在一个实施例中，该方法包括：在转换到集成电路（IC）的新状态之前，通过针对多个域中的每个域计算预期电流来计算IC中多个域的预期功率之和 在新状态的单个域频率上，将预期电流与其相关联的电压乘以用于新状态的多个域中的每一个; 将总和与功率限制进行比较; 并且如果所述和大于所述功率极限，则减少与所述多个域中的至少一个域相关联的各个域频率，以将所述IC的总瞬时功率维持在所述功率极限以下。
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公开(公告)号：US20170003725A1
公开(公告)日：2017-01-05
申请号：US15175741
申请日：2016-06-07
Applicant: Intel Corporation
Inventor： Nir Rosenzweig , Evgeny Bolotin , Guy Satat , Hisham Abu Salah
CPC classification number: G06F1/3203 , G06F1/26 , G06F1/324 , G06F9/38 , H03K3/0315 , H03L7/08 , Y02D10/126
Abstract: Interconnect frequency control technologies of adjusting an operating frequency of a communication interconnect between an integrated circuit comprising multiple functional hardware units are described. A power management unit (PMU) is configured to collect workload data from the functional hardware units and determine a workload metric from the workload data. The PMU adjusts an operating frequency of the communication interconnect in view of the workload metric.
Abstract translation: 描述了在包括多个功能硬件单元的集成电路之间调整通信互连的工作频率的互连频率控制技术。 电力管理单元（PMU）被配置为从功能硬件单元收集工作负载数据，并从工作负载数据确定工作负载度量。 PMU根据工作量度量调整通信互连的工作频率。
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