公开(公告)号：US20190163473A1

公开(公告)日：2019-05-30

申请号：US15824333

申请日：2017-11-28

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Mark Charney ,  Raanan Sade ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Roman S. Dubtsov

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F7/4806 ,  G06F7/4812 ,  G06F9/3013 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/382 ,  G06F9/3824 ,  G06F17/10

Abstract: An embodiment of the invention is a processor including execution circuitry to calculate, in response to a decoded instruction, a result of a complex multiplication of a first complex number and a second complex number. The calculation includes a first operation to calculate a first term of a real component of the result and a first term of the imaginary component of the result. The calculation also includes a second operation to calculate a second term of the real component of the result and a second term of the imaginary component of the result. The processor also includes a decoder, a first source register, and a second source register. The decoder is to decode an instruction to generate the decoded instruction. The first source register is to provide the first complex number and the second source register is to provide the second complex number.

公开(公告)号：US10303605B2

公开(公告)日：2019-05-28

申请号：US15214895

申请日：2016-07-20

Applicant: INTEL CORPORATION

Inventor： Raanan Sade ,  Joseph Nuzman ,  Stanislav Shwartsman ,  Igor Yanover ,  Liron Zur

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/0815 ,  G06F12/0893

Abstract: An example system on a chip (SoC) includes a processor, a cache, and a main memory. The SoC can include a first memory to store data in a memory line, wherein the memory line is set to an invalid state. The processor can include a processor coupled to the first memory. The processor can determine that a data size of a first data set received from an application is within a data size range. The processor can determine that an aggregate data size of the first data set and a second data set received from the application is at least a same data size as data size of the memory line. The processor can perform an invalid-to-modify (I2M) operation to change the memory line from the invalid state to a modified state. The processor can write the first data set and the second data set to the memory line.

公开(公告)号：US20190042255A1

公开(公告)日：2019-02-07

申请号：US15858937

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Simon Rubanovich ,  Amit Gradstein ,  Zeev Sperber ,  Alexander Heinecke ,  Robert Valentine ,  Mark J. Charney ,  Bret Toll ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall ,  Menachem Adelman

IPC: G06F9/30

Abstract: Embodiments detailed herein relate to systems and methods to store a tile register pair to memory. In one example, a processor includes: decode circuitry to decode a store matrix pair instruction having fields for an opcode and source and destination identifiers to identify source and destination matrices, respectively, each matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded store matrix pair instruction to store every element of left and right tiles of the identified source matrix to corresponding element positions of left and right tiles of the identified destination matrix, respectively, wherein the executing stores a chunk of C elements of one row of the identified source matrix at a time.

公开(公告)号：US20190042254A1

公开(公告)日：2019-02-07

申请号：US15858932

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Simon Rubanovich ,  Amit Gradstein ,  Zeev Sperber ,  Alexander Heinecke ,  Robert Valentine ,  Mark J. Charney ,  Bret Toll ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall ,  Menachem Adelman

IPC: G06F9/30

Abstract: Embodiments detailed herein relate to systems and methods to load a tile register pair. In one example, a processor includes: decode circuitry to decode a load matrix pair instruction having fields for an opcode and source and destination identifiers to identify source and destination matrices, respectively, each matrix having a PAIR parameter equal to TRUE; and execution circuitry to execute the decoded load matrix pair instruction to load every element of left and right tiles of the identified destination matrix from corresponding element positions of left and right tiles of the identified source matrix, respectively, wherein the executing operates on one row of the identified destination matrix at a time, starting with the first row.

公开(公告)号：US20190042235A1

公开(公告)日：2019-02-07

申请号：US15858916

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Raanan Sade ,  Simon Rubanovich ,  Amit Gradstein ,  Zeev Sperber ,  Alexander Heinecke ,  Robert Valentine ,  Mark J. Charney ,  Bret Toll ,  Jesus Corbal ,  Elmoustapha Ould-Ahmed-Vall ,  Menachem Adelman

IPC: G06F9/30

Abstract: Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (M,N) of the identified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the identified first source matrix by a corresponding nibble of a doubleword element (K,N) of the identified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element (M,N).

公开(公告)号：US20180210842A1

公开(公告)日：2018-07-26

申请号：US15416549

申请日：2017-01-26

Applicant: Intel Corporation

Inventor： Joseph Nuzman ,  Raanan Sade ,  Igor Yanover ,  Ron Gabor ,  Amit Gradstein

IPC: G06F12/1036

CPC classification number: G06F12/1036 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/657 ,  G06F2212/683 ,  G06F2212/684

Abstract: A processing device including a linear address transformation circuit to determine that a metadata value stored in a portion of a linear address falls within a pre-defined metadata range. The metadata value corresponds to a plurality of metadata bits. The linear address transformation circuit to replace each of the plurality of the metadata bits with a constant value.

公开(公告)号：US09558127B2

公开(公告)日：2017-01-31

申请号：US14481266

申请日：2014-09-09

Applicant: Intel Corporation

Inventor： Stanislav Shwartsman ,  Robert S. Chappell ,  Ronak Singhal ,  Ryan L. Carlson ,  Raanan Sade ,  Omar M. Shaikh ,  Liron Zur ,  Yiftach Gilad

IPC: G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0862 ,  G06F2212/1021 ,  G06F2212/402 ,  G06F2212/602

Abstract: A processor includes a cache hierarchy and an execution unit. The cache hierarchy includes a lower level cache and a higher level cache. The execution unit includes logic to issue a memory operation to access the cache hierarchy. The lower level cache includes logic to determine that a requested cache line of the memory operation is unavailable in the lower level cache, determine that a line fill buffer of the lower level cache is full, and initiate prefetching of the requested cache line from the higher level cache based upon the determination that the line fill buffer of the lower level cache is full. The line fill buffer is to forward miss requests to the higher level cache.

Abstract translation: 处理器包括缓存层级和执行单元。 高速缓存层级包括较低级别的缓存和较高级别的高速缓存。 执行单元包括发出存储器操作以访问高速缓存层级的逻辑。 下级高速缓存包括确定存储器操作的所请求的高速缓存行在下级高速缓存中不可用的逻辑，确定较低级高速缓存的行填充缓冲区已满，并且从较高级缓存启动所请求的高速缓存行的预取 基于下级缓存的行填充缓冲器的确定已满的高级缓存。 行填充缓冲区是将错误请求转发到更高级别的缓存。

公开(公告)号：US12287843B2

公开(公告)日：2025-04-29

申请号：US18502291

申请日：2023-11-06

Applicant: Intel Corporation

Inventor： Dan Baum ,  Chen Koren ,  Elmoustapha Ould-Ahmed-Vall ,  Michael Espig ,  Christopher J. Hughes ,  Raanan Sade ,  Robert Valentine ,  Mark J. Charney ,  Alexander F. Heinecke

IPC: G06F9/30 ,  G06F9/38 ,  G06F17/16

Abstract: Disclosed embodiments relate to accelerating multiplication of sparse matrices. In one example, a processor is to fetch and decode an instruction having fields to specify locations of first, second, and third matrices, and an opcode indicating the processor is to multiply and accumulate matching non-zero (NZ) elements of the first and second matrices with corresponding elements of the third matrix, and executing the decoded instruction as per the opcode to generate NZ bitmasks for the first and second matrices, broadcast up to two NZ elements at a time from each row of the first matrix and each column of the second matrix to a processing engine (PE) grid, each PE to multiply and accumulate matching NZ elements of the first and second matrices with corresponding elements of the third matrix. Each PE further to store an NZ element for use in a subsequent multiplications.

公开(公告)号：US12265826B2

公开(公告)日：2025-04-01

申请号：US18399014

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Bret Toll ,  Christopher J. Hughes ,  Dan Baum ,  Elmoustapha Ould-Ahmed-Vall ,  Raanan Sade ,  Robert Valentine ,  Mark J. Charney ,  Alexander F. Heinecke

IPC: G06F9/30

Abstract: Disclosed embodiments relate to systems for performing instructions to quickly convert and use matrices (tiles) as one-dimensional vectors. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode, locations of a two-dimensional (2D) matrix and a one-dimensional (1D) vector, and a group of elements comprising one of a row, part of a row, multiple rows, a column, part of a column, multiple columns, and a rectangular sub-tile of the specified 2D matrix, and wherein the opcode is to indicate a move of the specified group between the 2D matrix and the 1D vector, decode circuitry to decode the fetched instruction; and execution circuitry, responsive to the decoded instruction, when the opcode specifies a move from 1D, to move contents of the specified 1D vector to the specified group of elements.

公开(公告)号：US11977886B2

公开(公告)日：2024-05-07

申请号：US17706413

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Robert Valentine ,  Menachem Adelman ,  Elmoustapha Ould-Ahmed-Vall ,  Bret L. Toll ,  Milind B. Girkar ,  Zeev Sperber ,  Mark J. Charney ,  Rinat Rappoport ,  Jesus Corbal ,  Stanislav Shwartsman ,  Igor Yanover ,  Alexander F. Heinecke ,  Barukh Ziv ,  Dan Baum ,  Yuri Gebil ,  Raanan Sade

IPC: G06F9/30 ,  G06F7/485 ,  G06F7/487 ,  G06F7/76 ,  G06F9/38 ,  G06F17/16

CPC classification number: G06F9/30036 ,  G06F7/485 ,  G06F7/4876 ,  G06F7/762 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30134 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/30196 ,  G06F9/3818 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

Abstract: Embodiments detailed herein relate to matrix operations. In particular, the loading of a matrix (tile) from memory. For example, support for a loading instruction is described in at least a form of decode circuitry to decode an instruction having fields for an opcode, a source matrix operand identifier, and destination memory information, and execution circuitry to execute the decoded instruction to store each data element of configured rows of the identified source matrix operand to memory based on the destination memory information.