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    Reducing conflicts in direct mapped caches
    12.
    发明授权
    Reducing conflicts in direct mapped caches 有权

    公开(公告)号：US10296457B2

    公开(公告)日：2019-05-21

    申请号：US15474654

    申请日：2017-03-30

    Applicant: Intel Corporation

    Inventor： Ruchira Sasanka ,  Rajat Agarwal

    IPC: G06F12/0811 ,  G06F12/1009 ,  G06F12/1018 ,  G06F12/1027

    Abstract: A processor includes a processing core to execute a transaction with a memory via a cache and a cache controller, associated with the processor, comprising an index mapper circuit to identify a physical memory address associated with the transaction, wherein the physical memory address comprises a plurality of bits, determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value, determine, based on the tag value, a bit-placement order for combining the second set of bits and the third set of bits, combine, based on the bit-placement order, the second set of bits and the third set of bits to form an index, and generate, based on the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache, wherein the processing core is to access, based on the cache line, a memory location referenced by the physical memory address.

    Opportunistic increase of ways in memory-side cache
    13.
    发明授权
    Opportunistic increase of ways in memory-side cache 有权

    公开(公告)号：US10162758B2

    公开(公告)日：2018-12-25

    申请号：US15373701

    申请日：2016-12-09

    Applicant: INTEL CORPORATION

    Inventor： Ruchira Sasanka

    IPC: G06F12/128 ,  G06F12/0864 ,  G06F12/0811 ,  G06F12/0808

    Abstract: A processor includes a processor core and a cache controller coupled to the processor core. The cache controller is to allocate, for a memory, a plurality of cache entries in a cache, wherein the processor core is to: detect an amount of the memory installed in a computing system and, responsive to detecting less than a maximum allowable amount of the memory for the computing system, direct the cache controller to increase a number of ways of the cache in which to allocate the plurality of cache entries.

    Instruction and logic for cache control operations
    16.
    发明授权
    Instruction and logic for cache control operations 有权

    公开(公告)号：US10152421B2

    公开(公告)日：2018-12-11

    申请号：US14948830

    申请日：2015-11-23

    Applicant: Intel Corporation

    Inventor： Ruchira Sasanka

    IPC: G06F12/08 ,  G06F12/0875 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0888

    Abstract: In one embodiment, a processor includes: a fetch logic to fetch instructions; a decode logic to decode the instructions; a cache memory; and a control logic to receive a cache filter instruction and responsive to the cache filter instruction enable only a selected portion of a memory address space to be eligible to be cached in the cache memory. The cache filter instruction may indicate the selected portion of the memory address space. Other embodiments are described and claimed.

    REDUCING CONFLICTS IN DIRECT MAPPED CACHES
    17.
    发明申请
    REDUCING CONFLICTS IN DIRECT MAPPED CACHES 审中-公开

    公开(公告)号：US20180285267A1

    公开(公告)日：2018-10-04

    申请号：US15474654

    申请日：2017-03-30

    Applicant: Intel Corporation

    Inventor： Ruchira Sasanka ,  Rajat Agarwal

    IPC: G06F12/0811 ,  G06F12/1018 ,  G06F12/1027 ,  G06F12/1009

    CPC classification number: G06F12/0811 ,  G06F12/1009 ,  G06F12/1018 ,  G06F12/1027 ,  G06F2212/283 ,  G06F2212/65 ,  G06F2212/68

    Abstract: A processor includes a processing core to execute a transaction with a memory via a cache and a cache controller, associated with the processor, comprising an index mapper circuit to identify a physical memory address associated with the transaction, wherein the physical memory address comprises a plurality of bits, determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value, determine, based on the tag value, a bit-placement order for combining the second set of bits and the third set of bits, combine, based on the bit-placement order, the second set of bits and the third set of bits to form an index, and generate, based on the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache, wherein the processing core is to access, based on the cache line, a memory location referenced by the physical memory address.

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