公开(公告)号：US20240241839A1

公开(公告)日：2024-07-18

申请号：US18620523

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Anil kumar Nama ,  Usha ,  Kunal Ashwinkumar Shah ,  Manjunatha B M ,  Varsha Vithal Baikar ,  Shailendra Singh Chauhan ,  Muhammed Naseef Murikkumkadan

IPC: G06F13/10 ,  G06F3/14 ,  G06F3/147 ,  G06F9/4401

CPC classification number: G06F13/10 ,  G06F9/4418 ,  G06F3/1423 ,  G06F3/147

Abstract: Systems, apparatus, articles of manufacture, and methods for external display power loss detection and sleep state recovery are disclosed. Example apparatus disclosed herein include first circuitry to set an output of the first circuitry to a first logic value after a determination that a compute device is to enter a sleep state, and set the output to a second logic value after a determination that the compute device is to exit the sleep state. Disclosed example apparatus also include second circuitry to switch control of a hot plug detect (HPD) input of high-definition multimedia interface (HDMI) circuitry between an output of power loss sensing circuitry and an HPD line of an HDMI port of the HDMI circuitry based on the output of the first circuitry.

公开(公告)号：US20240102703A1

公开(公告)日：2024-03-28

申请号：US18163081

申请日：2023-02-01

Applicant: Intel Corporation

Inventor： Sreejith Satheesakurup ,  Rekha Bhagat ,  Shailendra Singh Chauhan

IPC: F25B21/02 ,  G06F1/20 ,  G06F1/3296 ,  H01L23/38

CPC classification number: F25B21/02 ,  G06F1/206 ,  G06F1/3296 ,  H01L23/38 ,  F25B2321/0212

Abstract: Systems, apparatuses and methods may provide for technology that includes a Peltier module and a subsystem thermally coupled and electrically coupled to the Peltier module, the subsystem to monitor an operational state of the subsystem, place the Peltier module in a first power mode if the operational state indicates that a demand spike exists with respect to the subsystem, and place the Peltier module in a second power mode if the operational state indicates that the demand spike does not exist with respect to the subsystem, wherein the second power mode is associated with a lower level of system power consumption than the first power mode.

公开(公告)号：US20240047986A1

公开(公告)日：2024-02-08

申请号：US17881433

申请日：2022-08-04

Applicant: Intel Corporation

Inventor： Ramesh Vankunavath ,  Shailendra Singh Chauhan ,  N.V.S Kumar Srighakollapu ,  Ankur Mishra

IPC: H02J7/00

CPC classification number: H02J7/00712 ,  H02J7/0042

Abstract: Techniques and mechanisms for improving an efficiency of power delivery resources. In one embodiment, switch circuitry is operated based on an indication from an integrated circuit (IC) die that circuitry of the IC die is ready to accommodate a low power state which disables a delivery of power to the IC die by a voltage regulator (VR). The switch circuitry is operated, based on a control signal is also used to disable said power delivery, to disable or otherwise prevent one or more conductive paths which are each between a respective two of a battery pack, a voltage regulator, or a battery charger. In another embodiment, the low power state enable a rail for circuitry which is to provide a real time clock signal to the IC die, but disables any other rails which power the IC die.

公开(公告)号：US20230384842A1

公开(公告)日：2023-11-30

申请号：US17825558

申请日：2022-05-26

Applicant: Intel Corporation

Inventor： Siva Prasad Jangili Ganga ,  Shailendra Singh Chauhan ,  Abhijith Prabha ,  Geejagaaru Krishnamurthy Sandesh ,  Santhosh Ap

IPC: G06F1/18 ,  H05K7/14 ,  G06F1/16 ,  H05K7/20

CPC classification number: G06F1/185 ,  H05K7/1422 ,  G06F1/1633 ,  H05K7/2039

Abstract: An electronic system has a printed circuit board and a substrate. The substrate has two sides, a top and bottom. At least one memory unit is connected to the bottom side of the substrate and at least one processor is connected to the top side of the substrate. The memory is connected to the processor with interconnects that pass through the substrate.

公开(公告)号：US20220107773A1

公开(公告)日：2022-04-07

申请号：US17552268

申请日：2021-12-15

Applicant: INTEL CORPORATION

Inventor： Arvind Tomar ,  Michael Hamann ,  Shailendra Singh Chauhan ,  Ratheesh Nair

IPC: G06F3/14 ,  G06F1/30 ,  G06F13/12

Abstract: Methods and apparatus for external display power loss detection. An example non-transitory computer readable medium comprises instructions that, when executed, cause a machine to at least determine whether a physical connection is established between a source device and an external display. In response to detecting the physical connection between the source device and the external display, present an application window from the source device to the external display, receive signal inputs from the external display, compare a first signal input from the signal inputs and second signal input from the signal inputs, and determine whether a calculated difference between the first signal input and the second signal input exceeds a threshold value. In response to determining that the calculated difference exceeds the threshold value, present the application window via the source device automatically without user input.

公开(公告)号：US12242859B2

公开(公告)日：2025-03-04

申请号：US17359512

申请日：2021-06-26

Applicant: INTEL CORPORATION

Inventor： Arthur Jeremy Runyan ,  Ratheesh Purushothaman Nair ,  Shailendra Singh Chauhan ,  Digant H. Solanki

IPC: G06F9/4401 ,  G06F1/3218 ,  G06F13/40

Abstract: Particular embodiments described herein provide for an electronic device that includes two or more displays and a BIOS. On startup, before the premem state and MRC initialization of the boot process, the BIOS causes power to be enabled to two or more displays. A display engine determines if a hot plug for each display is asserted and for each display where the hot plug was not asserted, the path to the display where the hot plug was not asserted is closed. In an example, the BIOS communicates the signal to power enable the first display and the second display after general-purpose input/output initialization during the boot process. After the premem stage and MRC initialization are completed, the first display and the second display are both configured to begin to display pixels.

公开(公告)号：US12242319B2

公开(公告)日：2025-03-04

申请号：US17482805

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Shailendra Singh Chauhan ,  Arunthathi Chandrabose

IPC: G06F1/26 ,  G06F1/3234 ,  H03F3/24

Abstract: An interface card includes a circuit board, a device mounted on the circuit board, and a PMIC mounted on the circuit board. The PMIC includes a PMIC processor communicatively coupled to a host processor of a host system. The PMIC processor is configured to receive an input voltage signal from a power supply that is external to the interface card. The PMIC processor generates at least one output voltage signal based on the input voltage signal. The at least one output voltage signal is supplied to the device. A power enable signal originating from the host processor is detected. The power enable signal is detected at a GPIO connector of the PMIC. The PMIC processor deactivates generation of the at least one output voltage signal based on the power enable signal.

公开(公告)号：US12212436B2

公开(公告)日：2025-01-28

申请号：US17398423

申请日：2021-08-10

Applicant: Intel Corporation

Inventor： Shailendra Singh Chauhan

IPC: H04L25/02 ,  H04L43/0864 ,  H04L43/0888

Abstract: A computing device includes a plurality of baseband processing circuitries. Each baseband processing circuitry of the plurality of baseband processing circuitries is configured to process signals for reception or transmission using a communication standard of a corresponding plurality of communication standards. The computing device further includes an application processor coupled to the plurality of baseband processing circuitries. The application processor is configured to determine a bandwidth of an application executing on the application processor of the computing device, determine a plurality of latencies associated with each baseband processing circuitry of the plurality of baseband processing circuitries, and select a baseband processing circuitry of the plurality of baseband processing circuitries to process transmit or receive data of the application based on the bandwidth and the plurality of latencies.

公开(公告)号：US20220417061A1

公开(公告)日：2022-12-29

申请号：US17398423

申请日：2021-08-10

Applicant: Intel Corporation

Inventor： Shailendra Singh Chauhan

IPC: H04L25/02 ,  H04L12/26

Abstract: A computing device includes a plurality of baseband processing circuitries. Each baseband processing circuitry of the plurality of baseband processing circuitries is configured to process signals for reception or transmission using a communication standard of a corresponding plurality of communication standards. The computing device further includes an application processor coupled to the plurality of baseband processing circuitries. The application processor is configured to determine a bandwidth of an application executing on the application processor of the computing device, determine a plurality of latencies associated with each baseband processing circuitry of the plurality of baseband processing circuitries, and select a baseband processing circuitry of the plurality of baseband processing circuitries to process transmit or receive data of the application based on the bandwidth and the plurality of latencies.