公开(公告)号：US20160299760A1

公开(公告)日：2016-10-13

申请号：US15131425

申请日：2016-04-18

Applicant: Intel Corporation

Inventor： Justin E. Gottschlich ,  Klaus Danne ,  Cristiano L. Pereira ,  Gilles A. Pokam ,  Rolf Kassa ,  Shiliang Hu ,  Tim Kranich

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/44 ,  G06F9/3005 ,  G06F9/30072 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/455 ,  G06F9/52 ,  G06F11/30 ,  G06F11/3414 ,  G06F11/3476 ,  G06F11/36 ,  G06F11/3664 ,  G06F11/3688 ,  G06F2201/815 ,  G06F2201/825 ,  G06F2201/865

Abstract: One or more embodiments may provide a method for performing a replay. The method includes initiating execution of a program, the program having a plurality of sets of instructions, and each set of instructions has a number of chunks of instructions. The method also includes intercepting, by a virtual machine unit executing on a processor, an instruction of a chunk of the number of chunks before execution. The method further includes determining, by a replay module executing on the processor, whether the chunk is an active chunk, and responsive to the chunk being the active chunk, executing the instruction.

Abstract translation: 一个或多个实施例可以提供用于执行重放的方法。 该方法包括启动程序的执行，程序具有多组指令，并且每组指令具有多个指令块。 该方法还包括通过在处理器上执行的虚拟机单元截取在执行之前块数量的指令。 该方法还包括通过在处理器上执行的重播模块确定该块是否是活动块，并且响应于该块作为活动块来执行该指令。

公开(公告)号：US09146844B2

公开(公告)日：2015-09-29

申请号：US13893238

申请日：2013-05-13

Applicant: INTEL CORPORATION

Inventor： Mauricio Breternitz ,  Youfeng Wu ,  Cheng Wang ,  Edson Borin ,  Shiliang Hu ,  Craig B. Zilles

IPC: G06F11/36 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F8/443 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466 ,  G06F11/3672 ,  G06F11/3688

Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

Abstract translation: 本文描述了用于有条件地提交和/或推测性检查点事务的装置和方法，这可能导致事务的动态调整大小。 在二进制代码的动态优化期间，插入事务以提供存储器排序保护措施，这使得动态优化器能够更积极地优化代码。 并且条件提交可以有效地执行动态优化代码，同时尝试防止事务用尽硬件资源。 虽然投机检查点能够在中止交易后快速有效地恢复。 处理器硬件适于支持事务的动态调整大小，诸如包括识别条件提交指令的解码器，推测性检查点指令或两者。 并且处理器硬件还适于执行响应于解码这样的指令来支持条件提交或推测性检查点的操作。

公开(公告)号：US10437319B2

公开(公告)日：2019-10-08

申请号：US14986678

申请日：2016-01-02

Applicant: Intel Corporation

Inventor： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC: G06F1/329 ,  G06F1/3287 ,  G06F9/38 ,  G06F9/50 ,  G06F11/34 ,  G06F9/445 ,  G06F9/48

Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

公开(公告)号：US10387296B2

公开(公告)日：2019-08-20

申请号：US14836103

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Youfeng Wu ,  Justin Gottschlich ,  Gilles Pokam ,  Shiliang Hu ,  Ali-Reza Adl-Tabatabai ,  Cristiano Pereira

IPC: G06F9/44 ,  G06F11/00 ,  G06F9/46 ,  G06F11/36 ,  G06F8/70 ,  G06F8/41 ,  G06F9/448

Abstract: Methods and systems to identify threads responsible for causing a concurrency bug in a computer program having a plurality of concurrently executing threads are disclosed. An example method disclosed herein includes defining, with a processor, a data type. The data type including a first predicate, the first predicate being invoked using a first program instruction inserted in a first thread of the plurality of threads, a second predicate, the second predicate being invoked using a second program instruction inserted in a second thread of the plurality of threads, and an expression defining a relationship between the first predicate and the second predicate. The method further includes, in response to determining the relationship is satisfied during execution of the computer program, identifying the first thread and the second thread as responsible for the concurrency bug.

公开(公告)号：US09965320B2

公开(公告)日：2018-05-08

申请号：US14142475

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Rolf Kassa ,  Justin E. Gottschlich ,  Shiliang Hu ,  Gilles A. Pokam ,  Robert C. Knauerhase

IPC: G06F9/46 ,  G06F15/00 ,  G06F9/52 ,  G06F11/07

CPC classification number: G06F9/467 ,  G06F9/528 ,  G06F11/0724 ,  G06F11/0772

Abstract: A processor is described comprising memory access conflict detection circuitry to identify a conflict pertaining to a transaction being executed by a thread that believes it has locked information within a memory. The processor also includes logging circuitry to construct and report out a packet if the memory access conflict detection circuitry identifies a conflict that causes the transaction to be aborted.

公开(公告)号：US09875108B2

公开(公告)日：2018-01-23

申请号：US13844817

申请日：2013-03-16

Applicant: Intel Corporation

Inventor： Gilles A. Pokam ,  Rolf Kassa ,  Klaus Danne ,  Tim Kranich ,  Cristiano L. Pereira ,  Justin E. Gottschlich ,  Shiliang Hu

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/32 ,  G06F12/0811 ,  G06F12/0842

CPC classification number: G06F9/3834 ,  G06F9/321 ,  G06F12/0811 ,  G06F12/0842 ,  Y02B70/12 ,  Y02D10/13

Abstract: A system, processor, and method to record the interleavings of shared memory accesses in the presence of complex multi-operation instructions. An extension to instruction atomicity (IA) is disclosed that makes it possible for software to infer partial information about a multi-operation execution if the hardware has recorded a dependency due to an instruction atomicity violation (IAV). By monitoring the progress of a multi-operation instruction, the need for complex multi-operation emulation is unnecessary.

公开(公告)号：US09817644B2

公开(公告)日：2017-11-14

申请号：US14867950

申请日：2015-09-28

Applicant: Intel Corporation

Inventor： Mauricio Breternitz, Jr. ,  Youfeng Wu ,  Cheng Wang ,  Edson Borin ,  Shiliang Hu ,  Craig B. Zilles

IPC: G06F9/45 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F11/36

CPC classification number: G06F8/443 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466 ,  G06F11/3672 ,  G06F11/3688

Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

公开(公告)号：US09697040B2

公开(公告)日：2017-07-04

申请号：US14226312

申请日：2014-03-26

Applicant: Intel Corporation

Inventor： Justin E. Gottschlich ,  Gilles A. Pokam ,  Shiliang Hu ,  Rolf Kassa ,  Youfeng Wu ,  Irina Calciu

IPC: G06F9/44 ,  G06F9/45 ,  G06F9/46 ,  G06F11/34 ,  G06F11/36

CPC classification number: G06F9/467 ,  G06F11/34 ,  G06F11/362 ,  G06F11/3648

Abstract: A system is disclosed that includes a processor and a dynamic random access memory (DRAM). The processor includes a hybrid transactional memory (HyTM) that includes hardware transactional memory (HTM), and a program debugger to replay a program that includes an HTM instruction and that has been executed has been executed using the HyTM. The program debugger includes a software emulator that is to replay the HTM instruction by emulation of the HTM. Other embodiments are disclosed and claimed.

公开(公告)号：US20150363306A1

公开(公告)日：2015-12-17

申请号：US14836103

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Youfeng Wu ,  Justin Gottschlich ,  Gilles Pokam ,  Shiliang Hu ,  Ali-Reza Adl-Tabatabai

IPC: G06F11/36 ,  G06F9/44

CPC classification number: G06F11/3688 ,  G06F8/434 ,  G06F8/70 ,  G06F9/448 ,  G06F11/36 ,  G06F11/3604 ,  G06F11/3612 ,  G06F11/3632 ,  G06F11/3636 ,  G06F11/3672

Abstract: Methods and systems to identify threads responsible for causing a concurrency bug in a computer program having a plurality of concurrently executing threads are disclosed. An example method disclosed herein includes defining, with a processor, a data type. The data type including a first predicate, the first predicate being invoked using a first program instruction inserted in a first thread of the plurality of threads, a second predicate, the second predicate being invoked using a second program instruction inserted in a second thread of the plurality of threads, and an expression defining a relationship between the first predicate and the second predicate. The method further includes, in response to determining the relationship is satisfied during execution of the computer program, identifying the first thread and the second thread as responsible for the concurrency bug.

Abstract translation: 公开了用于识别负责在具有多个同时执行的线程的计算机程序中引起并发错误的线程的方法和系统。 本文公开的示例性方法包括使用处理器来定义数据类型。 所述数据类型包括第一谓词，使用插入在所述多个线程的第一线程中的第一程序指令来调用所述第一谓词，第二谓词，所述第二谓词使用插入到所述第一线索的第二线程中的第二程序指令来调用 多个线程，以及定义第一谓词和第二谓词之间的关系的表达式。 该方法还包括响应于确定在执行计算机程序期间的关系得到满足，识别第一线程和第二线程，以负责并发错误。

公开(公告)号：US20140281382A1

公开(公告)日：2014-09-18

申请号：US13843940

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： James E. Smith ,  Denis M. Khartikov ,  Shiliang Hu ,  Youfeng Wu

IPC: G06F15/78

CPC classification number: G06F9/30 ,  G06F8/443 ,  G06F9/30181 ,  G06F9/328

Abstract: A system and method to enhance execution of architected instructions in a processor uses auxiliary code to optimize execution of base microcode. An execution context of the architected instructions may be profiled to detect potential optimizations, resulting in generation and storage of auxiliary microcode. When the architected instructions are decoded to base microcode for execution, the base microcode may be enhanced or modified using retrieved auxiliary code.

Abstract translation: 用于增强处理器中的架构指令执行的系统和方法使用辅助代码来优化基本微代码的执行。 可以对构建的指令的执行上下文进行分析以检测潜在的优化，从而产生和存储辅助微代码。 当结构化指令被解码为基本微代码以执行时，可以使用检索的辅助代码来增强或修改基本微代码。