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公开(公告)号：US11741030B2
公开(公告)日：2023-08-29
申请号：US17134242
申请日：2020-12-25
Applicant: Intel Corporation
Inventor： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC: G06F13/22 , H04L49/15 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , G06F9/46 , G06F13/40 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808 , H04L45/74 , G06F8/73 , H04L12/46
CPC classification number: G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4282 , G06F13/4286 , G06F13/4291 , H04L9/0662 , H04L49/15 , G06F8/73 , G06F13/4273 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L12/4641 , H04L45/74 , Y02D10/00 , Y02D30/00
Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
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公开(公告)号：US20190391939A1
公开(公告)日：2019-12-26
申请号：US16285035
申请日：2019-02-25
Applicant: Intel Corporation
Inventor： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC: G06F13/22 , G06F12/0808 , H04L9/06 , G06F13/42 , G06F11/10 , G06F13/40 , G06F1/3287 , G06F9/445 , G06F9/46 , G06F12/0831 , G06F12/0806 , G06F9/30 , G06F8/77 , G06F8/71 , G06F12/0815 , G06F12/0813 , H04L12/933
Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state
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公开(公告)号：US10216674B2
公开(公告)日：2019-02-26
申请号：US15393366
申请日：2016-12-29
Applicant: Intel Corporation
Inventor： Venkatraman Iyer , Darren S. Jue , Sitaraman V. Iyer
Abstract: A supersequence is generated that includes a sequence including an electrical ordered set (EOS) and a plurality of training sequences. The plurality of training sequences include a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.
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公开(公告)号：US09600431B2
公开(公告)日：2017-03-21
申请号：US13976919
申请日：2013-03-15
Applicant: Intel Corporation
Inventor： Venkatraman Iyer , Darren S. Jue , Sitaraman V. Iyer
CPC classification number: G06F13/4004 , G06F13/4221 , G06N99/005 , Y02D10/14 , Y02D10/151
Abstract: A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks.
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公开(公告)号：US20150205741A1
公开(公告)日：2015-07-23
申请号：US14672107
申请日：2015-03-28
Applicant: Intel Corporation
Inventor： Venkatraman Iyer , Darren S. Jue , Sitaraman V. Iyer
CPC classification number: G06F13/4004 , G06F13/4221 , G06N99/005 , Y02D10/14 , Y02D10/151
Abstract: A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks.
Abstract translation: 生成一组训练序列，每个训练序列包括相应的训练序列头部，训练序列头部将在训练序列集合上进行DC平衡。 训练序列的集合可以与电子有序集合组合以形成用于诸如链路适配，链路状态转换，字节锁定，偏斜校正和其他任务之类的任务的超序列。
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Patent Agency Ranking
公开(公告)号：US20220114122A1
公开(公告)日：2022-04-14
申请号：US17556853
申请日：2021-12-20
Applicant: Intel Corporation
Inventor： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC: G06F13/22 , H04L49/15 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , G06F9/46 , G06F13/40 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808
Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
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公开(公告)号：US11269793B2
公开(公告)日：2022-03-08
申请号：US16937499
申请日：2020-07-23
Applicant: Intel Corporation
Inventor： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
IPC: G06F13/22 , H04L49/15 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F13/42 , G06F8/71 , G06F8/77 , G06F9/30 , G06F12/0806 , G06F9/46 , G06F13/40 , G06F9/445 , G06F1/3287 , G06F11/10 , H04L9/06 , G06F12/0808 , H04L45/74 , G06F8/73 , H04L12/46
Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
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公开(公告)号：US10002095B2
公开(公告)日：2018-06-19
申请号：US14672107
申请日：2015-03-28
Applicant: Intel Corporation
Inventor： Venkatraman Iyer , Darren S. Jue , Sitaraman V. Iyer
CPC classification number: G06F13/4004 , G06F13/4221 , G06N20/00 , Y02D10/14 , Y02D10/151
Abstract: A set of training sequences is generated, each training sequence to include a respective training sequence header, and the training sequence header is to be DC-balanced over the set of training sequences. The set of training sequences can be combined with electric ordered sets to form supersequences for use in such tasks as link adaptation, link state transitions, byte lock, deskew, and other tasks.
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公开(公告)号：US20170109315A1
公开(公告)日：2017-04-20
申请号：US15393153
申请日：2016-12-28
Applicant: Intel Corporation
Inventor： Robert J. Safranek , Robert G. Blankenship , Venkatraman Iyer , Jeff Willey , Robert H. Beers , Darren S. Jue , Arvind A. Kumar , Debendra Das Sharma , Jeffrey C. Swanson , Bahaa Fahim , Vedaraman Geetha , Aaron T. Spink , Fulvio Spagna , Rahul R. Shah , Sitaraman V. Iyer , William Harry Nale , Abhishek Das , Simon P. Johnson , Yuvraj S. Dhillon , Yen-Cheng Liu , Raj K. Ramanujan , Robert A. Maddox , Herbert H. Hum , Ashish Gupta
CPC classification number: G06F13/22 , G06F1/3287 , G06F8/71 , G06F8/73 , G06F8/77 , G06F9/30145 , G06F9/44505 , G06F9/466 , G06F11/1004 , G06F12/0806 , G06F12/0808 , G06F12/0813 , G06F12/0815 , G06F12/0831 , G06F12/0833 , G06F13/4022 , G06F13/4068 , G06F13/4221 , G06F13/4273 , G06F13/4282 , G06F13/4286 , G06F13/4291 , G06F2212/1016 , G06F2212/2542 , G06F2212/622 , H04L9/0662 , H04L12/4641 , H04L45/74 , H04L49/15 , Y02D10/13 , Y02D10/14 , Y02D10/151 , Y02D10/40 , Y02D10/44 , Y02D30/30
Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.
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公开(公告)号：US20170085399A1
公开(公告)日：2017-03-23
申请号：US14863300
申请日：2015-09-23
Applicant: INTEL CORPORATION
Inventor： Salman Latif , Ravindran Mohanavelu , Sitaraman V. Iyer
CPC classification number: H04L25/03146 , H03M1/72 , H04L25/03006
Abstract: Embodiments include a pulsed decision feedback equalization (DFE) circuit. The DFE circuit may include a current integrating summer (CIS) circuit that passes one or more data signals on respective data nodes based on an input data signal and a clock signal. The DFE circuit may further include a correction circuit, such as a current digital-to-analog converter (IDAC) circuit, that may provide a correction circuit to a data node based on a prior bit of the input data signal. The correction circuit may provide a conductive path between a current source of the correction circuit and the data node for a time period that is less than the unit interval (UI) of the clock signal and/or data signal. The DFE circuit may include a plurality of correction circuits to provide respective correction signals based on different prior bits of the input data signal. Other embodiments may be described and claimed.
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