公开(公告)号：US09691657B2

公开(公告)日：2017-06-27

申请号：US15096609

申请日：2016-04-12

申请人： Intel Corporation

发明人： Hui Jae Yoo ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  James S. Clarke

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76849 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L2224/45015 ,  H01L2924/0002 ,  H01L2924/00011 ,  H01L2924/00

摘要： A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

公开(公告)号：US11881432B2

公开(公告)日：2024-01-23

申请号：US18088474

申请日：2022-12-23

申请人： Intel Corporation

发明人： Hui Jae Yoo ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  James S. Clarke

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76849 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/76882 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L21/76843 ,  H01L2224/45015 ,  H01L2924/0002 ,  H01L2224/45015 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

公开(公告)号：US11569126B2

公开(公告)日：2023-01-31

申请号：US17061062

申请日：2020-10-01

申请人： Intel Corporation

发明人： Hui Jae Yoo ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  James S. Clarke

IPC分类号： H01L21/768 ,  H01L23/532

摘要： A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

公开(公告)号：US10211098B2

公开(公告)日：2019-02-19

申请号：US16005175

申请日：2018-06-11

申请人： INTEL CORPORATION

发明人： Yuriy V. Shusterman ,  Flavio Griggio ,  Tejaswi K. Indukuri ,  Ruth A. Brain

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/528 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/31 ,  H01L23/532

摘要： Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.

公开(公告)号：US11328993B2

公开(公告)日：2022-05-10

申请号：US16881530

申请日：2020-05-22

申请人： Intel Corporation

发明人： Christopher J. Jezewski ,  Tejaswi K. Indukuri ,  Ramanan V. Chebiam ,  Colin T. Carver

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L29/49 ,  H01L29/78 ,  H01L23/522

摘要： An embodiment includes a metal interconnect structure, comprising: a dielectric layer disposed on a substrate; an opening in the dielectric layer, wherein the opening has sidewalls and exposes a conductive region of at least one of the substrate and an interconnect line; an adhesive layer, comprising manganese, disposed over the conductive region and on the sidewalls; and a fill material, comprising cobalt, within the opening and on a surface of the adhesion layer. Other embodiments are described herein.

公开(公告)号：US11094587B2

公开(公告)日：2021-08-17

申请号：US15570857

申请日：2015-06-03

申请人： Intel Corporation

发明人： Christopher J. Jezewski ,  Srijit Mukherjee ,  Daniel B. Bergstrom ,  Tejaswi K. Indukuri ,  Flavio Griggio ,  Ramanan V. Chebiam ,  James S. Clarke

IPC分类号： H01L23/48 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

摘要： In one embodiment, a conductive connector for a microelectronic component may be formed with a noble metal layer, acting as an adhesion/wetting layer, disposed between a barrier liner and a conductive fill material. In a further embodiment, the conductive connector may have a noble metal conductive fill material disposed directly on the barrier liner. The use of a noble metal as an adhesion/wetting layer or as a conductive fill material may improve gapfill and adhesion, which may result in the conductive connector being substantially free of voids, thereby improving the electrical performance of the conductive connector relative to conductive connectors without a noble metal as the adhesion/wetting layer or the conductive fill material.

公开(公告)号：US10658586B2

公开(公告)日：2020-05-19

申请号：US16099173

申请日：2016-07-02

申请人： Intel Corporation

发明人： James S. Clarke ,  Ravi Pillarisetty ,  Uday Shah ,  Tejaswi K. Indukuri ,  Niloy Mukherjee ,  Elijah V. Karpov ,  Prashant Majhi

IPC分类号： H01L45/00 ,  H01L27/24 ,  G11C13/00

摘要： Embodiments of the present invention include RRAM devices and their methods of fabrication. In an embodiment, a resistive random access memory (RRAM) cell includes a conductive interconnect disposed in a dielectric layer above a substrate. An RRAM device is coupled to the conductive interconnect. An RRAM memory includes a bottom electrode disposed above the conductive interconnect and on a portion of the dielectric layer. A conductive layer is formed on the bottom electrode layer. The conductive layer is separate and distinct from the bottom electrode layer. The conductive layer further includes a material that is different from the bottom electrode layer. A switching layer is formed on the conductive layer. An oxygen exchange layer is formed on the switching layer and a top electrode is formed on the oxygen exchange layer.

公开(公告)号：US10026649B2

公开(公告)日：2018-07-17

申请号：US15528425

申请日：2014-12-23

申请人： INTEL CORPORATION

发明人： Yuriy V. Shusterman ,  Flavio Griggio ,  Tejaswi K. Indukuri ,  Ruth A. Brain

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/532 ,  H01L21/3213 ,  H01L21/321 ,  H01L23/31 ,  H01L23/528

摘要： Techniques are disclosed for providing a decoupled via fill. Given a via trench, a first barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first metal fill is blanket deposited into the trench. The non-selective deposition is subsequently recessed so that only a portion of the trench is filled with the first metal. The previously deposited first barrier layer is removed along with the first metal, thereby re-exposing the upper sidewalls of the trench. A second barrier layer is conformally deposited onto the top of the first metal and the now re-exposed trench sidewalls. A second metal fill is blanket deposited into the remaining trench. Planarization and/or etching can be carried out as needed for subsequent processing. Thus, a methodology for filling high aspect ratio vias using a dual metal process is provided. Note, however, the first and second fill metals may be the same.