公开(公告)号：US20170337728A1

公开(公告)日：2017-11-23

申请号：US15156809

申请日：2016-05-17

Applicant: Intel Corporation

Inventor： Tomer Bar-On

IPC: G06T15/20 ,  G06T15/30 ,  G06T11/40 ,  G06T17/20 ,  G06T1/20

CPC classification number: G06T15/20 ,  G06T1/20 ,  G06T7/50 ,  G06T11/40 ,  G06T15/005 ,  G06T15/30 ,  G06T17/20

Abstract: A mechanism for efficient triangle rendering is described. A method of embodiments, as described herein, includes detecting a plurality of triangles during rendering of a digital image, computing an error bound as a function of depth value gradients and determining whether one or more of the plurality of triangles relative to a projection screen based on the error bound computation.

公开(公告)号：US20240177395A1

公开(公告)日：2024-05-30

申请号：US18324611

申请日：2023-05-26

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Tomer Bar-On ,  Gabor Liktor ,  Andrew T. Lauritzen ,  John G. Gierach

IPC: G06T15/00 ,  G06T15/30 ,  G06T15/40

CPC classification number: G06T15/005 ,  G06T15/30 ,  G06T15/40

Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.

公开(公告)号：US20240004833A1

公开(公告)日：2024-01-04

申请号：US18349386

申请日：2023-07-10

Applicant: Intel Corporation

Inventor： Altug Koker ,  Prasoonkumar Surti ,  David Puffer ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Abhishek R. Appu ,  Joydeep Ray ,  Balaji Vembu ,  Tomer Bar-On ,  Andrew T. Lauritzen ,  Hugues Labbe ,  John G. Gierach ,  Gabor Liktor

IPC: G06F16/13 ,  G06F9/38 ,  G06F9/30 ,  G06F16/11 ,  G06F16/172 ,  G06F9/46

CPC classification number: G06F16/13 ,  G06F9/3836 ,  G06F9/30 ,  G06F9/38 ,  G06F16/113 ,  G06F16/172 ,  G06F9/461 ,  G06F2201/84 ,  G06F12/1036

Abstract: In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

公开(公告)号：US11704856B2

公开(公告)日：2023-07-18

申请号：US17529938

申请日：2021-11-18

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Tomer Bar-On ,  Gabor Liktor ,  Andrew T. Lauritzen ,  John G. Gierach

IPC: G06T15/00 ,  G06T15/30 ,  G06T15/40

CPC classification number: G06T15/005 ,  G06T15/30 ,  G06T15/40

Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.

公开(公告)号：US11688366B2

公开(公告)日：2023-06-27

申请号：US17461228

申请日：2021-08-30

Applicant: Intel Corporation

Inventor： Travis Schluessler ,  Abhishek Venkatesh ,  John Gierach ,  Tomer Bar-On ,  Devan Burke

IPC: G06T15/40 ,  G09G5/36 ,  G09G5/391 ,  G06T15/20 ,  G06T7/70 ,  G06T15/00 ,  G09G3/00 ,  G06T1/20 ,  G09G5/00 ,  G06T3/00 ,  G09G5/397 ,  G06T1/60 ,  G09G5/377 ,  G06F3/14

CPC classification number: G09G5/363 ,  G06T1/20 ,  G06T7/70 ,  G06T15/005 ,  G06T15/20 ,  G06T15/405 ,  G09G3/003 ,  G09G5/001 ,  G09G5/391 ,  G06F3/1446 ,  G06T1/60 ,  G06T3/0093 ,  G06T2210/08 ,  G06T2210/36 ,  G06T2210/52 ,  G09G5/377 ,  G09G5/397 ,  G09G2300/026 ,  G09G2320/0252 ,  G09G2330/023 ,  G09G2340/0407 ,  G09G2340/0428 ,  G09G2352/00 ,  G09G2354/00 ,  G09G2360/06 ,  G09G2360/08 ,  G09G2360/121 ,  G09G2360/122

Abstract: Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

公开(公告)号：US11656846B2

公开(公告)日：2023-05-23

申请号：US17103179

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Yaniv Fais ,  Tomer Bar-On ,  Jacob Subag ,  Jeremie Dreyfuss ,  Lev Faivishevsky ,  Michael Behar ,  Amit Bleiweiss ,  Guy Jacob ,  Gal Leibovich ,  Itamar Ben-Ari ,  Galina Ryvchin ,  Eyal Yaacoby

IPC: G06F7/533 ,  G06N20/00 ,  G06T1/20

CPC classification number: G06F7/5332 ,  G06N20/00 ,  G06T1/20

Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.

公开(公告)号：US11354848B1

公开(公告)日：2022-06-07

申请号：US16662636

申请日：2019-10-24

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer Kp ,  Jonathan Kennedy ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Tomer Bar-On ,  Carsten Benthin ,  Adam T. Lake ,  Vasanth Ranganathan ,  Abhishek R. Appu

IPC: G06T15/08 ,  G06K9/00 ,  H04N5/369 ,  G06T15/60 ,  G06T15/10 ,  H04N13/239 ,  H04N13/344 ,  H04N5/232 ,  G02B27/01 ,  G06T15/00

Abstract: Systems, apparatuses and methods may provide for technology that assigns a first shading rate to a first region of a frame. The technology further assigns a second shading rate to a second region of the frame. The first shading rate indicates that the first region will be rendered at a first resolution, and the second shading rate indicates that the second region will be rendered at a second resolution less than the first resolution. The first and second shading rates are associated with a selection based on a motion vector that corresponds to motion of an object. The object is rendered as part of a scene that includes the first region rendered at the first resolution and the second region rendered at the second resolution.

公开(公告)号：US20220005259A1

公开(公告)日：2022-01-06

申请号：US17481656

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Atsuo Kuwahara ,  Hugues Labbe ,  Sameer KP ,  Jonathan Kennedy ,  Joydeep Ray ,  Travis T. Schluessler ,  John H. Feit ,  Nikos Kaburlasos ,  Jacek Kwiatkowski ,  Tomer Bar-On ,  Carsten Benthin ,  Adam T. Lake ,  Vasanth Ranganathan ,  Abhishek R. Appu

IPC: G06T15/08 ,  G06K9/00 ,  G02B27/01 ,  G06T15/60 ,  H04N5/232 ,  H04N13/344 ,  G06T15/10 ,  H04N5/369 ,  G06T15/00 ,  H04N13/239

Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

公开(公告)号：US11093822B2

公开(公告)日：2021-08-17

申请号：US15499896

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Uzi Sarel ,  Ehud Cohen ,  Tomer Schwartz ,  Amitai Armon ,  Yahav Shadmiy ,  Amit Bleiweiss ,  Gal Leibovich ,  Jeremie Dreyfuss ,  Lev Faivishevsky ,  Tomer Bar-On ,  Yaniv Fais ,  Jacob Subag

IPC: G06N3/063 ,  G06F9/30 ,  G06N3/04 ,  G06N3/08

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210150798A1

公开(公告)日：2021-05-20

申请号：US17127740

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Hugues Labbe ,  Tomer Bar-On ,  Gabor Liktor ,  Andrew T. Lauritzen ,  John G. Gierach

IPC: G06T15/00 ,  G06T15/30 ,  G06T15/40

Abstract: Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.