公开(公告)号：US20190243701A1

公开(公告)日：2019-08-08

申请号：US15890893

申请日：2018-02-07

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Ki W. Yoon ,  Michael J. St. Clair ,  Larisa Novakovsky ,  Hisham Shafi ,  William H. Penner ,  Yoni Aizik ,  Kevin Safford ,  Hermann Gartler

IPC: G06F11/07 ,  G06F9/38

Abstract: Embodiment of this disclosure provides a mechanism to support hang detection and data recovery in microprocessor systems. In one embodiment, a processing device comprising a processing core and a crashlog unit operatively coupled to the core is provided. An indication of an unresponsive state in an execution of a pending instruction by the core is received. Responsive to receiving the indication, a crash log comprising data from registers of at least one of: a core region, a non-core region and a controller hub associated with the processing device is produced. Thereupon, the crash log is stored in a shared memory of a power management controller (PMC) associated with the controller hub.

公开(公告)号：US09910475B2

公开(公告)日：2018-03-06

申请号：US14580553

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Beeman C. Strong ,  Richard B. O'Connor ,  Michael W. Chynoweth ,  Rajshree A. Chabukswar ,  Avner Lottem ,  Itamar Kazachinsky ,  Michael Mishaeli ,  Anthony Wojciechowski ,  Vikas R. Vasisht

IPC: G06F1/32 ,  G06F11/30 ,  G06F11/34

CPC classification number: G06F1/3206 ,  G06F11/3024 ,  G06F11/3055 ,  G06F11/348 ,  G06F2201/86

Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.

公开(公告)号：US09716646B2

公开(公告)日：2017-07-25

申请号：US14334071

申请日：2014-07-17

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Beeman C. Strong ,  Ofer Levy ,  Gabi Malka ,  Zeev Sperber

IPC: H04L7/00 ,  H04L12/26 ,  H04J3/06

CPC classification number: H04L43/50 ,  H04J3/0664 ,  H04L43/106

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for using thresholds to gate timing packet generation in a tracing system (TS). For example, the method may include generating and outputting a trace data (TD) packet into a packet log. The method also includes generating and outputting a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.

公开(公告)号：US09696997B2

公开(公告)日：2017-07-04

申请号：US14992658

申请日：2016-01-11

Applicant: INTEL CORPORATION

Inventor： Tsvika Kurts ,  Ofer Levy ,  Itamar Kazachinsky ,  Gabi Malka ,  Zeev Sperber ,  Jason W. Brandt

IPC: G06F9/00 ,  G06F7/38 ,  G06F9/30 ,  G06F11/00 ,  G06F11/36 ,  G06F11/34 ,  G06F13/40

CPC classification number: G06F9/30145 ,  G06F11/00 ,  G06F11/3471 ,  G06F11/36 ,  G06F13/4068 ,  G06F2201/865

Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.

公开(公告)号：US20170149554A1

公开(公告)日：2017-05-25

申请号：US14950319

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Ernest Knoll ,  Ofer Nathan ,  Michael Mishaeli ,  Krishnakanth V. Sistla ,  Ariel Sabba ,  Shani Rehana ,  Ariel Szapiro ,  Tsvika Kurts ,  Ofer Levy

IPC: H04L7/033 ,  H04L7/00

CPC classification number: H04L7/0331 ,  G06F1/08 ,  G06F1/10 ,  G06F1/324 ,  H04L7/0025 ,  H04L7/005 ,  Y02D10/126

Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.

公开(公告)号：US11085964B2

公开(公告)日：2021-08-10

申请号：US16403296

申请日：2019-05-03

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Boris Dolgunov ,  Vladislav Mladentsev ,  Ittai Anati ,  Elias Khoury ,  Maor Kima ,  Eran Shlomo ,  Shay Gueron ,  William Penner

IPC: G01R31/317 ,  G06F16/22 ,  G01R31/3177 ,  G06F11/263 ,  H04L9/06 ,  H04L9/08 ,  H04L9/32

Abstract: Systems and techniques of the present disclosure may provide remote debugging of an integrated circuit (IC) device while preventing unauthorized access of device intellectual property (IP). A system may include an IC device that generates an encrypted session key and an interface that enables communication between the IC device and a remote debugging site. The interface may enable the IC device to send the encrypted the encrypted session key to initiate a remote debug process, receive an acknowledgement from the remote debugging session, and authenticate the acknowledgement. Further, the interface may enable to the IC device to initiate a secure debug session between the IC device and the remote debugging site.

公开(公告)号：US10656697B2

公开(公告)日：2020-05-19

申请号：US15911577

申请日：2018-03-05

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Beeman C. Strong ,  Richard B. O'Connor ,  Michael W. Chynoweth ,  Rajshree A. Chabukswar ,  Avner Lottem ,  Itamar Kazachinsky ,  Michael Mishaeli ,  Anthony Wojciechowski ,  Vikas R. Vasisht

IPC: G06F1/32 ,  G06F11/34 ,  G06F11/30 ,  G06F1/3206

Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.

公开(公告)号：US10372642B2

公开(公告)日：2019-08-06

申请号：US15279762

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Yanir Oz ,  Tsvika Kurts

IPC: G06F13/37

Abstract: In one embodiment, a distributed arbitration system for an interconnect includes: a first transmitter to output first data and a transmit identifier associated with the first data; and a first arbiter coupled to the first transmitter to receive the first data and to arbitrate between the first data and second data from a second arbiter coupled to the first arbiter, based at least in part on a change in a state of the transmit identifier. Other embodiments are described and claimed.

公开(公告)号：US20190050041A1

公开(公告)日：2019-02-14

申请号：US15911577

申请日：2018-03-05

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Beeman C. Strong ,  Richard B. O'Connor ,  Michael W. Chynoweth ,  Rajshree A. Chabukswar ,  Avner Lottem ,  Itamar Kazachinsky ,  Michael Mishaeli ,  Anthony Wojciechowski ,  Vikas R. Vasisht

IPC: G06F1/32 ,  G06F11/34 ,  G06F11/30

Abstract: A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.

公开(公告)号：US09262163B2

公开(公告)日：2016-02-16

申请号：US13730834

申请日：2012-12-29

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Ofer Levy ,  Itamar Kazachinsky ,  Gabi Malka ,  Zeev Sperber ,  Jason W. Brandt

IPC: G06F7/38 ,  G06F9/00 ,  G06F9/30

CPC classification number: G06F9/30145 ,  G06F11/00 ,  G06F11/3471 ,  G06F11/36 ,  G06F13/4068 ,  G06F2201/865

Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.

Abstract translation: 一方面的方法包括为处理器的第一逻辑处理器生成实时指令跟踪（RTIT）分组。 RTIT分组指示由第一逻辑处理器执行的软件的流程。 RTIT分组被存储在对应于第一逻辑处理器的RTIT队列中。 RTIT数据包主要通过处理器的固件从RTIT队列传送到存储器。 还公开了其它方法，装置和系统。