公开(公告)号：US09817644B2

公开(公告)日：2017-11-14

申请号：US14867950

申请日：2015-09-28

Applicant: Intel Corporation

Inventor： Mauricio Breternitz, Jr. ,  Youfeng Wu ,  Cheng Wang ,  Edson Borin ,  Shiliang Hu ,  Craig B. Zilles

IPC: G06F9/45 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F11/36

CPC classification number: G06F8/443 ,  G06F8/52 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30116 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/466 ,  G06F11/3672 ,  G06F11/3688

Abstract: An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic resizing of transactions. During dynamic optimization of binary code, transactions are inserted to provide memory ordering safeguards, which enables a dynamic optimizer to more aggressively optimize code. And the conditional commit enables efficient execution of the dynamic optimization code, while attempting to prevent transactions from running out of hardware resources. While the speculative checkpoints enable quick and efficient recovery upon abort of a transaction. Processor hardware is adapted to support dynamic resizing of the transactions, such as including decoders that recognize a conditional commit instruction, a speculative checkpoint instruction, or both. And processor hardware is further adapted to perform operations to support conditional commit or speculative checkpointing in response to decoding such instructions.

公开(公告)号：US09710391B2

公开(公告)日：2017-07-18

申请号：US13886467

申请日：2013-05-03

Applicant: Intel Corporation

Inventor： Wei Liu ,  Youfeng Wu ,  Christopher Wilkerson ,  Herbert Hum

IPC: G06F15/00 ,  G06F12/0888 ,  G06F9/45 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F12/0888 ,  G06F8/4442 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/383 ,  Y02D10/13

Abstract: Various embodiments of the invention concern methods and apparatuses for power and time efficient load handling. A compiler may identify producer loads, consumer reuse loads, consumer forwarded loads, and producer/consumer hybrid loads. Based on this identification, performance of the load may be efficiently directed to a load value buffer, store buffer, data cache, or elsewhere. Consequently, accesses to cache are reduced, through direct loading from load value buffers and store buffers, thereby efficiently processing the loads.

公开(公告)号：US09697040B2

公开(公告)日：2017-07-04

申请号：US14226312

申请日：2014-03-26

Applicant: Intel Corporation

Inventor： Justin E. Gottschlich ,  Gilles A. Pokam ,  Shiliang Hu ,  Rolf Kassa ,  Youfeng Wu ,  Irina Calciu

IPC: G06F9/44 ,  G06F9/45 ,  G06F9/46 ,  G06F11/34 ,  G06F11/36

CPC classification number: G06F9/467 ,  G06F11/34 ,  G06F11/362 ,  G06F11/3648

Abstract: A system is disclosed that includes a processor and a dynamic random access memory (DRAM). The processor includes a hybrid transactional memory (HyTM) that includes hardware transactional memory (HTM), and a program debugger to replay a program that includes an HTM instruction and that has been executed has been executed using the HyTM. The program debugger includes a software emulator that is to replay the HTM instruction by emulation of the HTM. Other embodiments are disclosed and claimed.

公开(公告)号：US20160378679A1

公开(公告)日：2016-12-29

申请号：US14751454

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Marcelo S. Cintra ,  Cheng Wang ,  Youfeng Wu ,  Alexandre Xavier DuChateau

IPC: G06F12/10 ,  G06F12/02

CPC classification number: G06F12/1009 ,  G06F8/447 ,  G06F9/3836 ,  G06F9/44568 ,  G06F12/0238 ,  G06F12/0292 ,  G06F2212/1044

Abstract: Technologies for persistent memory pointer access include a computing device having a persistent memory including one or more nonvolatile regions. The computing device may load a persistent memory pointer having a static region identifier, a segment identifier, and an offset from the persistent memory. The computing device may map the static region identifier to a dynamic region identifier and determine a virtual memory address of the persistent memory pointer target based on the dynamic region identifier, the segment identifier, and the offset. The computing device may load an in-storage representation of a persistent-export pointer from the persistent memory, map the in-storage representation to a runtime representation, and determine a target address of a persistent external data object based on the runtime representation. The computing device may include a compiler to generate output code including persistent memory pointer and/or persistent-export pointer accesses. Other embodiments are described and claimed.

Abstract translation: 用于持久存储器指针访问的技术包括具有包括一个或多个非易失性区域的持久存储器的计算设备。 计算设备可以从永久存储器加载具有静态区域标识符，段标识符和偏移的持久存储器指针。 计算设备可以将静态区域标识符映射到动态区域标识符，并且基于动态区域标识符，段标识符和偏移来确定持久存储器指针目标的虚拟存储器地址。 计算设备可以从永久存储器加载持久输出指针的存储器表示，将存储器表示映射到运行时表示，并且基于运行时表示来确定持久外部数据对象的目标地址。 计算设备可以包括用于生成包括持久存储器指针和/或持久输出指针访问的输出代码的编译器。 描述和要求保护其他实施例。

公开(公告)号：US09239712B2

公开(公告)日：2016-01-19

申请号：US13853430

申请日：2013-03-29

Applicant: Intel Corporation

Inventor： Hongbo Rong ,  Hyunchul Park ,  Youfeng Wu

IPC: G06F9/45

CPC classification number: G06F8/4452 ,  G06F8/433

Abstract: Apparatuses and methods may provide for determining a level of performance for processing one or more loops by a dynamic compiler and executing code optimizations to generate a pipelined schedule for the one or more loops that achieves the determined level of performance within a prescribed time period. In one example, a dependence graph may be established for the one or more loops, and each dependence graph may be partitioned into stages based on the level of performance.

Abstract translation: 设备和方法可以提供用于通过动态编译器来确定用于处理一个或多个循环的性能水平，并且执行代码优化以生成用于在规定时间段内实现所确定的性能水平的所述一个或多个循环的流水线调度。 在一个示例中，可以为一个或多个循环建立依赖图，并且可以基于性能水平将每个依赖图划分成多个阶段。

公开(公告)号：US20150363306A1

公开(公告)日：2015-12-17

申请号：US14836103

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Youfeng Wu ,  Justin Gottschlich ,  Gilles Pokam ,  Shiliang Hu ,  Ali-Reza Adl-Tabatabai

IPC: G06F11/36 ,  G06F9/44

CPC classification number: G06F11/3688 ,  G06F8/434 ,  G06F8/70 ,  G06F9/448 ,  G06F11/36 ,  G06F11/3604 ,  G06F11/3612 ,  G06F11/3632 ,  G06F11/3636 ,  G06F11/3672

Abstract: Methods and systems to identify threads responsible for causing a concurrency bug in a computer program having a plurality of concurrently executing threads are disclosed. An example method disclosed herein includes defining, with a processor, a data type. The data type including a first predicate, the first predicate being invoked using a first program instruction inserted in a first thread of the plurality of threads, a second predicate, the second predicate being invoked using a second program instruction inserted in a second thread of the plurality of threads, and an expression defining a relationship between the first predicate and the second predicate. The method further includes, in response to determining the relationship is satisfied during execution of the computer program, identifying the first thread and the second thread as responsible for the concurrency bug.

Abstract translation: 公开了用于识别负责在具有多个同时执行的线程的计算机程序中引起并发错误的线程的方法和系统。 本文公开的示例性方法包括使用处理器来定义数据类型。 所述数据类型包括第一谓词，使用插入在所述多个线程的第一线程中的第一程序指令来调用所述第一谓词，第二谓词，所述第二谓词使用插入到所述第一线索的第二线程中的第二程序指令来调用 多个线程，以及定义第一谓词和第二谓词之间的关系的表达式。 该方法还包括响应于确定在执行计算机程序期间的关系得到满足，识别第一线程和第二线程，以负责并发错误。

公开(公告)号：US20150363242A1

公开(公告)日：2015-12-17

申请号：US14833315

申请日：2015-08-24

Applicant: Intel Corporation

Inventor： Justin E. Gottschlich ,  Cristiano Ligieri Pereira ,  Gilles Pokam ,  Youfeng Wu

IPC: G06F9/52

CPC classification number: G06F9/52 ,  G06F11/3632

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to manage concurrent predicate expressions. An example method discloses inserting a first condition hook into a first thread, the first condition hook associated with a first condition, inserting a second condition hook into a second thread, the second condition hook associated with a second condition, preventing the second thread from executing until the first condition is satisfied, and identifying a concurrency violation when the second condition is satisfied.

Abstract translation: 公开了方法，装置，系统和制品以管理并发谓词表达。 一种示例性方法公开了将第一条件钩插入到第一线程中，与第一条件相关联的第一条件钩，将第二条件钩插入到第二线程中，与第二条件相关联的第二条件钩，防止第二线程执行 直到满足第一条件，并且当满足第二条件时识别并发冲突。

公开(公告)号：US20140281382A1

公开(公告)日：2014-09-18

申请号：US13843940

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： James E. Smith ,  Denis M. Khartikov ,  Shiliang Hu ,  Youfeng Wu

IPC: G06F15/78

CPC classification number: G06F9/30 ,  G06F8/443 ,  G06F9/30181 ,  G06F9/328

Abstract: A system and method to enhance execution of architected instructions in a processor uses auxiliary code to optimize execution of base microcode. An execution context of the architected instructions may be profiled to detect potential optimizations, resulting in generation and storage of auxiliary microcode. When the architected instructions are decoded to base microcode for execution, the base microcode may be enhanced or modified using retrieved auxiliary code.

Abstract translation: 用于增强处理器中的架构指令执行的系统和方法使用辅助代码来优化基本微代码的执行。 可以对构建的指令的执行上下文进行分析以检测潜在的优化，从而产生和存储辅助微代码。 当结构化指令被解码为基本微代码以执行时，可以使用检索的辅助代码来增强或修改基本微代码。

公开(公告)号：US20140223166A1

公开(公告)日：2014-08-07

申请号：US14169955

申请日：2014-01-31

Applicant: INTEL CORPORATION

Inventor： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC: G06F9/445

CPC classification number: G06F1/329 ,  G06F1/3287 ,  G06F9/3851 ,  G06F9/445 ,  G06F9/4893 ,  G06F9/5027 ,  G06F9/5094 ,  G06F11/3409 ,  G06F11/3452 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/865 ,  G06F2201/88 ,  G06F2209/501 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/34 ,  Y02D50/20

Abstract: Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a second processing core may be signaled. A first performance metric of the first processing core executing the program code may be collected. When the first performance metric is better than a previously determined core performance metric, power down of the second processing core may be signaled and execution of the program code may be continued on the first processing core. When the first performance metric is not better than the previously determined core performance metric, execution of the program code may be switched from the first processing core to the second processing core.

Abstract translation: 可以通过在第一处理核上执行程序代码来执行异构多核处理系统上的动态切换核。 可以用信号通知第二处理核心的加电。 可以收集执行程序代码的第一处理核心的第一性能度量。 当第一性能指标优于先前确定的核心性能指标时，可以发信号通知第二处理核心的掉电，并且可以在第一处理核心上继续执行程序代码。 当第一性能度量不比先前确定的核心性能指标更好时，程序代码的执行可以从第一处理核心切换到第二处理核心。

公开(公告)号：US20220326756A1

公开(公告)日：2022-10-13

申请号：US17852066

申请日：2022-06-28

Applicant: Intel Corporation

Inventor： Youfeng Wu ,  Shiliang Hu ,  Edson Borin ,  Cheng Wang

IPC: G06F1/329 ,  G06F1/3287 ,  G06F9/38 ,  G06F9/50 ,  G06F11/34 ,  G06F9/445 ,  G06F9/48

Abstract: Example methods and apparatus to facilitate dynamic core selection are disclosed. An example apparatus includes a first processor core of a first type; a second processor core of a second type different from the first type; and software to: access a user-supplied hint indicative of a user preference to execute program code on the first processor core, the user-supplied hint including a user-defined attribute of the program code; monitor performance of the program code on the first processor core; determine, based on the user-defined attribute of the program code, a predicted performance of the program code on the second processor core is better than the performance of the program code on the first processor core; and ignore the user preference by migrating the program code from the first processor core for execution on the second processor core