中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.019 seconds)

    Digital-to-time converter spur reduction
    13.
    发明授权
    Digital-to-time converter spur reduction 有权

    公开(公告)号：US09768809B2

    公开(公告)日：2017-09-19

    申请号：US14318829

    申请日：2014-06-30

    Applicant: Intel IP Corporation

    Inventor： Stefan Tertinek ,  Peter Preyler ,  Thomas Mayer

    IPC: H04B1/00 ,  H04B7/06 ,  H04W88/06 ,  H04L27/14 ,  G04F10/00

    CPC classification number: H04B1/0082 ,  G04F10/005

    Abstract: This application discusses, among other things, apparatus and methods for improving spurious frequency performance of digital-to-time converters (DTCs). In an example, a method can include receiving a code at selection logic of a digital-to-time converter at a first instant, selecting a first delay path of the DTC to provide a delay associated with the code, associating a second delay path with the code, receiving the code at the selection logic at a second instant, and selecting the second delay path of the DTC to provide the delay associated with the code.

    PHASE TRACKER FOR A PHASE LOCKED LOOP
    14.
    发明申请
    PHASE TRACKER FOR A PHASE LOCKED LOOP 有权
    相位锁相环的相位跟踪器

    公开(公告)号：US20160087639A1

    公开(公告)日：2016-03-24

    申请号：US14494718

    申请日：2014-09-24

    Applicant: Intel IP Corporation

    Inventor： Christian Wicpalek ,  Thomas Mayer ,  Andreas Mayer ,  Thorsten Tracht

    IPC: H03L7/085 ,  G04F10/00

    CPC classification number: H03L7/085 ,  G04F10/005 ,  H03L7/1976

    Abstract: A phase locked loop includes a feedforward path receiving a reference signal having a reference frequency and outputting an output signal having an output frequency that is a function of the reference signal and a feedback signal. The phase locked loop further includes a feedback path having a divider circuit associated therewith that is configured to receive the output signal and generate the feedback signal having a reduced frequency based on a divide value of the divider circuit. The feedback signal is supplied to the feedforward path. The phase locked loop also includes a modulator circuit configured to receive modulation data and provide a divider control signal to the divider circuit to control the divide value thereof, and a phase tracker circuit configured to determine an amount of phase drift from an initial phase value of the output signal due to an interruption in a locked state of the phase locked loop.

    Abstract translation: 锁相环包括接收具有参考频率的参考信号的前馈路径，并输出具有作为参考信号和反馈信号的函数的输出频率的输出信号。 锁相环还包括具有与其相关联的分频器电路的反馈路径，其被配置为接收输出信号并且基于分频器电路的除法产生具有降低的频率的反馈信号。 反馈信号被提供给前馈路径。 锁相环还包括配置成接收调制数据并将分频器控制信号提供给分频器电路以控制其分频值的调制器电路，以及相位跟踪器电路，被配置为从相位漂移的初始相位值 该输出信号由于锁相环中的锁定状态而中断。

    CIRCUIT, AN INTEGRATED CIRCUIT, A TRANSMITTER, A RECEIVER, A TRANSCEIVER, A METHOD FOR OBTAINING CALIBRATION DATA AND A METHOD FOR GENERATING A LOCAL OSCILLATOR SIGNAL
    16.
    发明申请
    CIRCUIT, AN INTEGRATED CIRCUIT, A TRANSMITTER, A RECEIVER, A TRANSCEIVER, A METHOD FOR OBTAINING CALIBRATION DATA AND A METHOD FOR GENERATING A LOCAL OSCILLATOR SIGNAL 有权
    电路，集成电路，发送器，接收器，收发器，用于获取校准数据的方法和用于产生本地振荡器信号的方法

    公开(公告)号：US20150280842A1

    公开(公告)日：2015-10-01

    申请号：US14620488

    申请日：2015-02-12

    Applicant: Intel IP Corporation

    Inventor： Thomas Mayer ,  Stefan Tertinek ,  Peter Preyler

    IPC: H04B17/21 ,  H04B1/62

    CPC classification number: H04B17/21 ,  H03L7/1976 ,  H04B1/62

    Abstract: A circuit according to an example includes a digital-to-time converter and a signal processing circuit coupled to the digital-to-time converter and configured to generate a processed signal derived from a signal provided to the signal processing circuit, the processed signal including a predetermined phase relation with respect to the signal provided to the signal processing circuit, wherein the circuit is configured to receive a reference signal and to generate an output signal based on the received reference signal. The a measurement circuit is configured to measure a delay between the output signal and the reference signal, wherein the output of the digital-to-time converter is coupled to a memory configured to store calibration data of the digital-to-time converter based on the measured delay.

    Abstract translation: 根据示例的电路包括数字 - 时间转换器和耦合到数字 - 时间转换器并被配置为产生从提供给信号处理电路的信号导出的处理信号的信号处理电路，处理信号包括 相对于提供给信号处理电路的信号的预定相位关系，其中电路被配置为接收参考信号并且基于接收到的参考信号产生输出信号。 测量电路被配置为测量输出信号和参考信号之间的延迟，其中数字 - 时间转换器的输出耦合到存储器，该存储器被配置为存储数字 - 时间转换器的校准数据，基于 测量延迟。

Patent Agency Ranking