公开(公告)号：US20150318182A1

公开(公告)日：2015-11-05

申请号：US14268098

申请日：2014-05-02

Applicant: International Business Machines Corporation ,  ZEON Corporation

Inventor： Eric A. Joseph ,  Goh Matsuura ,  Masahiro Nakamura ,  Edmund M. Sikorski ,  Bang N. To

IPC: H01L21/3065 ,  H01L21/308

CPC classification number: H01L21/3065 ,  H01L21/30655 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/768 ,  H01L21/76898

Abstract: Pretreatment of an etch chamber for performing a silicon etch process and Bosch process can be effected by running a deposition process employing C5HF7, or by running an alternating deposition and etch process employing C5H2F6 and SF6. It has been discovered that the pretreatment of the etch chamber for the silicon etch process can enhance the etch rate of silicon by at least 50% without adverse effect on etch profile during a first each process following the pretreatment, while the etch rate enhancement factor decreases over time. By periodically performing the pretreatment in the etch chamber, the throughput of the etch chamber can be increased without adversely impacting the etch profile of the processed substrates.

Abstract translation: 用于执行硅蚀刻工艺和Bosch工艺的蚀刻室的预处理可以通过运行采用C5HF7的沉积工艺，或者通过运行采用C5H2F6和SF6的交替沉积和蚀刻工艺来实现。 已经发现，用于硅蚀刻工艺的蚀刻室的预处理可以在预处理之后的第一个每个处理期间将硅的蚀刻速率提高至少50％，而不会对蚀刻轮廓产生不利影响，而蚀刻速率增强因子减小 随着时间的推移。 通过在蚀刻室中周期性地执行预处理，可以增加蚀刻室的生产量，而不会不利地影响经处理的基板的蚀刻轮廓。

公开(公告)号：US20150243602A1

公开(公告)日：2015-08-27

申请号：US14711872

申请日：2015-05-14

Applicant: International Business Machines Corporation

Inventor： Cyril Cabral, JR. ,  Benjamin L. Fletcher ,  Nicholas C.M. Fuller ,  Eric A. Joseph ,  Hiroyuki Miyazoe

IPC: H01L23/535 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/02109 ,  H01L21/31111 ,  H01L21/32131 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76852 ,  H01L21/76856 ,  H01L21/76885 ,  H01L21/823871 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have pitches of less than one hundred nanometers and sidewall tapers of between approximately eighty and ninety degrees. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the layer of conductive metal using a methanol plasma, wherein a portion of the layer of conductive metal that remains after the sputter etching forms the one or more conductive lines.

Abstract translation: 集成电路的一个实施例包括多个半导体器件和连接多个半导体器件的多条导线，其中多条导线中的至少一些具有小于百纳米的间距，以及约八十 和九十度。 集成电路的另一实施例包括多个半导体器件和连接多个半导体器件的多条导线，其中通过提供多层结构中的导电金属层来制造多条导线中的至少一些 制造在晶片上并使用甲醇等离子体溅射蚀刻导电金属层，其中在溅射蚀刻之后保留的导电金属层的一部分形成一个或多个导电线。

公开(公告)号：US20140183668A1

公开(公告)日：2014-07-03

申请号：US14013598

申请日：2013-08-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Eric A. Joseph ,  Satyavolu S. Papa Rao

IPC: H01L29/66 ,  G01N33/543

CPC classification number: H01L29/66007 ,  B01L3/502707 ,  G01N33/48721 ,  G01N33/54373 ,  H01L29/66

Abstract: A pair of electrode plates can be provided by directional deposition and patterning of a conductive material on sidewalls of a template structure on a first dielectric layer. An electrode line straddling the center portion is formed. A dielectric spacer and a conformal conductive layer are subsequently formed. Peripheral electrodes laterally spaced from the electrode line are formed by pattering the conformal conductive layer. After deposition of a second dielectric material layer that encapsulates the template structure, the template structure is removed to provide a cavity that passes through the pair of electrode plates, the electrode line, and the peripheral electrodes. A nanoscale sensor thus formed can electrically characterize a nanoscale string by passing the nanoscale string through the cavity while electrical measurements are performed employing the various electrodes.

公开(公告)号：US20140154862A1

公开(公告)日：2014-06-05

申请号：US14174777

申请日：2014-02-06

Applicant: Macronix International Co., Ltd. ,  International Business Machines Corporation

Inventor： Matthew J. Breitwisch ,  Roger W. Cheek ,  Chung H. Lam ,  Hsiang-Lan Lung ,  Eric A. Joseph ,  Alejandro G. Schrott

IPC: H01L45/00

CPC classification number: H01L45/1683 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148

Abstract: A memory cell and a method of making the same, that includes insulating material deposited on a substrate, a bottom electrode formed within the insulating material, a plurality of insulating layers deposited above the bottom electrode and at least one of which acts as an intermediate insulating layer. A via is defined in the insulating layers above the intermediate insulating layer. A channel is created for etch with a sacrificial spacer. A pore is defined in the intermediate insulating layer. All insulating layers above the intermediate insulating layer are removed, and the entirety of the remaining pore is filled with phase change material. An upper electrode is formed above the phase change material.

Abstract translation: 存储单元及其制造方法，其包括沉积在基板上的绝缘材料，形成在绝缘材料内的底部电极，沉积在底部电极上方的多个绝缘层，并且其中至少一个用作中间绝缘层 层。 在中间绝缘层上方的绝缘层中限定通孔。 创建一个通道用于用牺牲隔离物进行蚀刻。 在中间绝缘层中限定孔。 除去中间绝缘层之上的所有绝缘层，并且剩余的孔的整个填充有相变材料。 在相变材料上形成上电极。

公开(公告)号：US08633117B1

公开(公告)日：2014-01-21

申请号：US13671186

申请日：2012-11-07

Applicant: International Business Machines Corporation

Inventor： Cyril Cabral ,  Benjamin L. Fletcher ,  Nicholas C. M. Fuller ,  Eric A. Joseph ,  Hiroyuki Miyazoe

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L23/535 ,  H01L21/02109 ,  H01L21/31111 ,  H01L21/32131 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76852 ,  H01L21/76856 ,  H01L21/76885 ,  H01L21/823871 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, fabricating conductive lines in an integrated circuit includes providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the conductive metal using methanol plasma, wherein a portion of the conductive metal that remains after the sputter etching forms the conductive lines. In another embodiment, fabricating conductive lines in an integrated circuit includes providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer, wherein the layer of conductive metal is an intermediate layer in the multi-layer structure, etching the multi-layer structure to expose the conductive metal, sputter etching conductive metal using methanol plasma, wherein a portion of the conductive metal that remains after the sputter etching forms the conductive lines, forming a liner that surrounds the conductive lines, subsequent to the sputter etching, and depositing a dielectric layer on the multi-layer structure.

Abstract translation: 在一个实施例中，在集成电路中制造导线包括提供制造在晶片上的多层结构中的导电金属层，并使用甲醇等离子体溅射蚀刻导电金属，其中在溅射之后保留的部分导电金属 蚀刻形成导电线。 在另一个实施例中，在集成电路中制造导线包括提供制造在晶片上的多层结构中的导电金属层，其中导电金属层是多层结构中的中间层， 层结构以暴露导电金属，使用甲醇等离子体溅射蚀刻导电金属，其中在溅射蚀刻之后保留的部分导电金属形成导电线，形成围绕导电线的衬垫，在溅射蚀刻之后，以及 在多层结构上沉积介电层。

公开(公告)号：US10727114B2

公开(公告)日：2020-07-28

申请号：US15405440

申请日：2017-01-13

Applicant: International Business Machines Corporation

Inventor： Robert L. Bruce ,  Alfred Grill ,  Eric A. Joseph ,  Teddie P. Magbitang ,  Hiroyuki Miyazoe ,  Deborah A. Neumayer

IPC: H01L23/52 ,  H01L21/768 ,  H01L23/532

Abstract: Integrated circuits including at least two electrically conductive interconnect lines and methods of manufacturing generally include a surface of the integrated circuit. At least two electrically conductive interconnect lines are separated by a space of less than 90 nm and are formed on the surface. Each of the at least two interconnect lines includes a metal cap, a copper conductor having an average grain size greater than a line width of the interconnect. A liner layer is provided, wherein the liner layer and the metal cap encapsulate the copper conductor. A dielectric layer overlaying the at least two electrically conductive interconnect lines and extending along sidewalls thereof is provided, wherein the dielectric layer is configured to provide an airgap between the at least two interconnect lines at the spacing.

公开(公告)号：US10600656B2

公开(公告)日：2020-03-24

申请号：US15818947

申请日：2017-11-21

Applicant: International Business Machines Corporation

Inventor： Eric A. Joseph ,  Hiroyuki Miyazoe ,  Adam M. Pyzyna ,  HsinYu Tsai

IPC: H01L21/00 ,  H01L21/3213 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L27/24

Abstract: A process for forming patterned copper lines, a pattern of copper lines, and an electronic device having patterned copper lines and at least one CMOS circuit. The process includes assembling an etch stack, wherein the etch stack includes a resist and a copper substrate. The process also includes lithographically patterning the resist to produce a template, and forming a patterned block copolymer mask layer by directed self-assembly. Additionally, the process includes etching portions of the block copolymer mask layer to produce a patterned block copolymer mask layer, and transferring a pattern formed by the template and the patterned block copolymer mask layer to the copper substrate to form the patterned copper lines.

公开(公告)号：US20190172762A1

公开(公告)日：2019-06-06

申请号：US15833866

申请日：2017-12-06

Applicant: International Business Machines Corporation

Inventor： Sebastian U. Engelmann ,  Eric A. Joseph

IPC: H01L21/66 ,  H01L21/311

Abstract: A method of forming integrated circuit (IC) chips. After masking a layer of a material to be etched, the layer is subjected to an atomic layer etch (ALE). During the ALE, etch effluent is measured with a calorimetric probe. The calorimetric probe results reflect a species of particles resulting from etching the material. The measured etch results are checked until the results indicate the particle content is below a threshold value. When the content is below the threshold ALE is complete and IC chip fabrication continues normally.

公开(公告)号：US20190157106A1

公开(公告)日：2019-05-23

申请号：US15818947

申请日：2017-11-21

Applicant: International Business Machines Corporation

Inventor： Eric A. Joseph ,  Hiroyuki Miyazoe ,  Adam M. Pyzyna ,  HsinYu Tsai

IPC: H01L21/3213 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

Abstract: A process for forming patterned copper lines, a pattern of copper lines, and an electronic device having patterned copper lines and at least one CMOS circuit. The process includes assembling an etch stack, wherein the etch stack includes a resist and a copper substrate. The process also includes lithographically patterning the resist to produce a template, and forming a patterned block copolymer mask layer by directed self-assembly. Additionally, the process includes etching portions of the block copolymer mask layer to produce a patterned block copolymer mask layer, and transferring a pattern formed by the template and the patterned block copolymer mask layer to the copper substrate to form the patterned copper lines.

公开(公告)号：US20190096757A1

公开(公告)日：2019-03-28

申请号：US16201448

申请日：2018-11-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robert L. Bruce ,  Cyril Cabral, JR. ,  Gregory M. Fritz ,  Eric A. Joseph ,  Michael F. Lofaro ,  Hiroyuki Miyazoe ,  Kenneth P. Rodbell ,  Ghavam Shahidi

IPC: H01L21/768

CPC classification number: H01L21/76885 ,  H01L21/76852 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.