公开(公告)号：US20240319584A1

公开(公告)日：2024-09-26

申请号：US18189185

申请日：2023-03-23

Applicant: International Business Machines Corporation

Inventor： Pouya Hashemi ,  Steven Holmes ,  Robert L. Bruce ,  Eric A. Joseph ,  Yanning Sun

IPC: G03F7/00

CPC classification number: G03F7/0002 ,  G03F7/0015 ,  G03F7/0035

Abstract: A semiconductor structure includes a plurality of mandrel structures disposed above and in contact with a substrate. Each of the plurality of mandrel structures extending outwardly at an inclination angle with respect to a surface plane of the substrate that is different from 90 degrees. A template structure for an imprint mask is formed by the plurality of mandrel structures. The semiconductor structure further includes a layer of a conformal dielectric material covering the plurality of mandrel structures for providing stability and uniformity to the plurality of mandrel structures.

公开(公告)号：US20190013209A1

公开(公告)日：2019-01-10

申请号：US16130596

申请日：2018-09-13

Applicant: International Business Machines Corporation ,  Zeon Corporation

Inventor： Robert L. Bruce ,  Eric A. Joseph ,  Joe Lee ,  Takefumi Suzuki

IPC: H01L21/311 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528

Abstract: In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.

公开(公告)号：US10170698B2

公开(公告)日：2019-01-01

申请号：US15590545

申请日：2017-05-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony J. Annunziata ,  Armand A. Galan ,  Steve Holmes ,  Eric A. Joseph ,  Gen P. Lauer ,  Qinghuang Lin ,  Nathan P. Marchack

IPC: G03F7/20 ,  H01L43/12 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L27/22

Abstract: A method of forming a pillar includes masking a photoresist material using a reticle and a developer having a polarity opposite that of the photoresist to provide an island of photoresist material. A layer under the island of photoresist material is etched to establish a pillar defined by the island of photoresist material.

公开(公告)号：US10121676B2

公开(公告)日：2018-11-06

申请号：US15847369

申请日：2017-12-19

Applicant: International Business Machines Corporation ,  Zeon Corporation

Inventor： Robert L. Bruce ,  Eric A. Joseph ,  Joe Lee ,  Takefumi Suzuki

IPC: H01L29/06 ,  H01L29/40 ,  H01L21/311 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.

公开(公告)号：US09728421B2

公开(公告)日：2017-08-08

申请号：US14985951

申请日：2015-12-31

Applicant: International Business Machines Corporation

Inventor： Markus Brink ,  Sebastian U. Engelmann ,  Eric A. Joseph ,  Hiroyuki Miyazoe

IPC: H01L21/311 ,  H01L21/02

CPC classification number: H01L21/31116 ,  H01L21/02321 ,  H01L21/31144

Abstract: A method of etching a pattern into a dielectric layer is provided. An organic planarization layer having a pattern is provided atop a dielectric layer. A cyclic fluorocarbon deposition step and plasma step is performed to etch the pattern into the dielectric layer. The energy for the plasma step is kept below the etch threshold of the dielectric layer.

公开(公告)号：US09646881B2

公开(公告)日：2017-05-09

申请号：US15157891

申请日：2016-05-18

Applicant: International Business Machines Corporation

Inventor： Robert L. Bruce ,  Gregory M. Fritz ,  Eric A. Joseph ,  Hiroyuki Miyazoe

IPC: H01L21/3213 ,  H01L21/768 ,  H01L21/288 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L23/528 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53252 ,  H01L24/05 ,  H01L2224/05025 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147

Abstract: In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.

公开(公告)号：US20170062707A1

公开(公告)日：2017-03-02

申请号：US15184109

申请日：2016-06-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony J. Annunziata ,  Armand A. Galan ,  Steve Holmes ,  Eric A. Joseph ,  Gen P. Lauer ,  Qinghuang Lin ,  Nathan P. Marchack

IPC: H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  H01L43/02

CPC classification number: H01L43/12 ,  G03F7/70325 ,  G03F7/70425 ,  G11C11/161 ,  G11C2211/5615 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive memory cell includes a magnetic tunnel junction pillar having a circular cross section. The pillar has a pinned magnetic layer, a tunnel barrier layer, and a free magnetic layer. A first conductive contact is disposed above the magnetic tunnel junction pillar. A second conductive contact is disposed below the magnetic tunnel junction pillar.

Abstract translation: 磁阻存储单元包括具有圆形横截面的磁隧道连接柱。 该柱具有钉扎磁性层，隧道势垒层和自由磁性层。 第一导电触点设置在磁隧道结柱的上方。 第二导电触点设置在磁隧道结柱的下方。

公开(公告)号：US20170040257A1

公开(公告)日：2017-02-09

申请号：US14817783

申请日：2015-08-04

Applicant: International Business Machines Corporation

Inventor： Robert L. Bruce ,  Gregory M. Fritz ,  Eric A. Joseph ,  Hiroyuki Miyazoe

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/2885 ,  H01L21/32133 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53252 ,  H01L24/05 ,  H01L2224/05025 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147

Abstract: In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.

公开(公告)号：US20160379869A1

公开(公告)日：2016-12-29

申请号：US14749811

申请日：2015-06-25

Applicant: International Business Machines Corporation

Inventor： Stephen M. Gates ,  Gregory M. Fritz ,  Eric A. Joseph ,  Terry A. Spooner

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76814 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76888 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53266

Abstract: A semiconductor device and a method of fabricating a contact to interface with an interconnect in a semiconductor device are described. The device includes a dielectric layer formed on a semiconductor layer, and a contact fabricated in a via formed within the dielectric layer. An interconnect formed above the contact interfaces with an exposed surface of the contact opposite a surface closest to the semiconductor layer. The contact includes a contact material in a first portion of the contact and an interface metal in a second portion of the contact.

公开(公告)号：US20150348832A1

公开(公告)日：2015-12-03

申请号：US14289422

申请日：2014-05-28

Applicant: International Business Machines Corporation

Inventor： Robert L. Bruce ,  Cyril Cabral, JR. ,  Gregory M. Fritz ,  Eric A. Joseph ,  Michael F. Lofaro ,  Hiroyuki Miyazoe ,  Kenneth P. Rodbell ,  Ghavam G. Shahidi

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76885 ,  H01L21/76852 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.

Abstract translation: 本公开涉及集成电路和制造集成电路互连的方法。 例如，集成电路包括集成电路的表面和形成在表面上并且包括金属的互连。 互连金属的平均晶粒尺寸大于或等于互连线宽的至少一半。 在另一示例中，用于制造集成电路的互连的方法包括将金属层沉积到集成电路的表面上，退火金属，图案化第一硬掩模以放置在金属上并形成互连线 以及通过使用第一硬掩模执行对金属的定时蚀刻的互连的第一通孔。