公开(公告)号：US20180074111A1

公开(公告)日：2018-03-15

申请号：US15805406

申请日：2017-11-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Mukta G. Farooq ,  John A. Griesemer ,  Chandrasekaran Kothandaraman ,  John M. Safran ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: G01R31/08 ,  H01L21/66 ,  H01L23/48

CPC classification number: G01R31/08 ,  G01R31/2856 ,  G01R31/2858 ,  H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure, such as a wafer, semiconductor chip, integrated circuit, or the like, includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV) incldues at least one perimeter sidewall. The EM monitor includes a first EM wire separated from the perimeter sidewall of the TSV by a dielectric

公开(公告)号：US09893023B2

公开(公告)日：2018-02-13

申请号：US15606178

申请日：2017-05-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Edward C. Cooney, III ,  Fen Chen ,  Jonathan M. Pratt ,  Jason P. Ritter ,  Patrick S. Spinney ,  Anna Tilley

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L23/573 ,  H01L21/76895 ,  H01L23/5226 ,  H01L2224/11

Abstract: A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent.

公开(公告)号：US09453873B2

公开(公告)日：2016-09-27

申请号：US14154505

申请日：2014-01-14

Applicant: International Business Machines Corporation

Inventor： Fen Chen ,  Roger A. Dufresne ,  Kevin Kolvenbach ,  Michael A. Shinosky

IPC: G01R31/26

CPC classification number: G01R31/2623

Abstract: Disclosed are test structures and methods for non-planar field effect transistors. The test structures comprise test device(s) on an insulator layer. Each device comprises semiconductor fin(s). Each fin has a first portion comprising a pseudo channel region at one end and a second portion comprising a diffusion region positioned laterally adjacent to the first portion. A gate with sidewall spacers can be adjacent to the first portion of the fin(s). A first contact can be on the insulator layer adjacent the end of the fin(s). A second contact can be on the second portion of the fin(s) such that the gate is positioned laterally between the contacts. Measurements taken when the first contact is biased against the gate are compared to measurements taken when the second contact is biased against the gate in order to assess lateral dielectric breakdown between the gate and first contact independent of gate dielectric breakdown.

Abstract translation: 公开了非平面场效应晶体管的测试结构和方法。 测试结构包括绝缘体层上的测试装置。 每个装置包括半导体鳍片。 每个翅片具有包括在一端的伪通道区域的第一部分和包括位于横向相邻于第一部分的扩散区域的第二部分。 具有侧壁间隔件的门可以与鳍的第一部分相邻。 第一接触可以在与鳍的端部相邻的绝缘体层上。 第二触点可以在鳍的第二部分上，使得栅极横向定位在触点之间。 将第一接触件偏压到栅极时进行的测量与第二接触件相对于栅极偏置时的测量值进行比较，以便评估栅极和第一接触件之间的横向电介质击穿，而与栅极绝缘击穿无关。

公开(公告)号：US09230914B2

公开(公告)日：2016-01-05

申请号：US14526741

申请日：2014-10-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Trevor A. Thompson ,  Eric J. White

IPC: H01L27/08 ,  H01L29/00 ,  H01L21/76 ,  H01L23/52 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76843 ,  H01L21/2885 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

公开(公告)号：US20150115460A1

公开(公告)日：2015-04-30

申请号：US14065454

申请日：2013-10-29

Applicant: International Business Machines Corporation

Inventor： Fen Chen ,  Minhua Lu ,  Timothy D. Sullivan ,  Ping-Chuan Wang ,  Lijuan Zhang

IPC: H01L23/48 ,  H01L23/522

CPC classification number: H01L23/481 ,  H01L23/5226 ,  H01L2224/11 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure generally provides for integrated circuit (IC) structures with through-semiconductor vias (TSV). In an embodiment, an IC structure may include a through-semiconductor via (TSV) embedded in a substrate, the TSV having a cap; a dielectric layer adjacent to the substrate; a metal layer adjacent to the dielectric layer; a plurality of vias each embedded within the dielectric layer and coupling the metal layer to the cap of the TSV at respective contact points, wherein the plurality of vias is configured to create a substantially uniform current density throughout the TSV.

Abstract translation: 本公开通常提供具有贯穿半导体通孔（TSV）的集成电路（IC）结构。 在一个实施例中，IC结构可以包括嵌入在衬底中的贯穿半导体通孔（TSV），TSV具有帽; 与基板相邻的电介质层; 与介电层相邻的金属层; 多个通孔，每个通孔嵌入在电介质层内，并将金属层耦合到各个接触点处的TSV的盖，其中多个通孔被配置成在整个TSV中产生基本均匀的电流密度。

公开(公告)号：US20140339558A1

公开(公告)日：2014-11-20

申请号：US13895605

申请日：2013-05-16

Applicant: International Business Machines Corporation

Inventor： Fen Chen ,  Cathryn J. Christiansen ,  Roger A. Dufresne

IPC: H01L23/498 ,  H01L21/66 ,  H01L23/544

CPC classification number: H01L22/32 ,  H01L22/14 ,  H01L22/34 ,  H01L23/49827 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Kerf areas are located between the integrated circuit chips on a wafer. Via chain test structures are located in the kerf areas or test chips. The via chain test structures comprise a first conductor in a first area of the wafer. First via chains are connected at individual points to the first conductor. Each of the first via chains comprises an open-ended electrical circuit beginning at the first conductor and ending in an insulated region of a second area of the wafer. The via chain test structures comprise a second conductor in the second area. Second via chains are connected at individual points to the second conductor. Each of the second via chains comprises an open-ended electrical circuit beginning at the second conductor and ending in an insulated region of the first area.

Abstract translation: Kerf区域位于晶片上的集成电路芯片之间。 通过链条测试结构位于切口区域或测试芯片中。 通孔链测试结构包括在晶片的第一区域中的第一导体。 首先通过链条在各个点处连接到第一导体。 第一通孔链中的每一个包括从第一导体开始并在晶片的第二区域的绝缘区域结束的开放式电路。 通孔链测试结构包括第二区域中的第二导体。 第二通道链在各个点处连接到第二导体。 每个第二通孔链包括从第二导体开始并且终止于第一区域的绝缘区域的开放式电路。

公开(公告)号：US08779491B2

公开(公告)日：2014-07-15

申请号：US13772493

申请日：2013-02-21

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Fen Chen ,  Baozhen Li

IPC: H01L27/108

CPC classification number: H01L23/5223 ,  H01L21/76805 ,  H01L25/0657 ,  H01L28/91 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.

Abstract translation: 本发明提供一种3D通孔电容器及其形成方法。 电容器包括在基板上的绝缘层。 绝缘层具有通孔，其具有侧壁和底部。 第一电极覆盖通孔的侧壁和底部的至少一部分。 第一高k电介质材料层覆盖在第一电极上。 第一导电板在第一高k电介质材料层之上。 第二高k电介质材料层覆盖在第一导电板上并留下未填充的通孔的剩余部分。 在通孔的剩余部分中形成第二电极。 第一导电板基本上平行于第一电极并且不与第一和第二电极接触。 还提供了这种3D通孔电容器的阵列。

公开(公告)号：US20130161791A1

公开(公告)日：2013-06-27

申请号：US13772493

申请日：2013-02-21

Applicant: International Business Machines Corporation

Inventor： Chih-Chao Yang ,  Fen Chen ,  Baozhen Li

IPC: H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/76805 ,  H01L25/0657 ,  H01L28/91 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a 3D via capacitor and a method for forming the same. The capacitor includes an insulating layer on a substrate. The insulating layer has a via having sidewalls and a bottom. A first electrode overlies the sidewalls and at least a portion of the bottom of the via. A first high-k dielectric material layer overlies the first electrode. A first conductive plate is over the first high-k dielectric material layer. A second high-k dielectric material layer overlies the first conductive plate and leaves a remaining portion of the via unfilled. A second electrode is formed in the remaining portion of the via. The first conductive plate is substantially parallel to the first electrode and is not in contact with the first and second electrodes. An array of such 3D via capacitors is also provided.

公开(公告)号：US10545110B2

公开(公告)日：2020-01-28

申请号：US16392055

申请日：2019-04-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Fen Chen ,  Jeffrey P. Gambino ,  Carole D. Graas ,  Wen Liu ,  Prakash Periasamy

IPC: G01N27/22 ,  G01R27/26 ,  G01D5/24 ,  H03K17/955

Abstract: Moisture detection and ingression monitoring systems and methods of manufacture are provided. The moisture detection structure includes chip edge sealing structures including at least one electrode forming a capacitor structured to detect moisture ingress within an integrated circuit. The at least one electrode and a second electrode of the capacitor is biased to ground and to a moisture detection circuit or vice versa, respectively.

公开(公告)号：US09059052B2

公开(公告)日：2015-06-16

申请号：US13895605

申请日：2013-05-16

Applicant: International Business Machines Corporation

Inventor： Fen Chen ,  Cathryn J. Christiansen ,  Roger A. Dufresne

IPC: G01R31/26 ,  H01L21/66

CPC classification number: H01L22/32 ,  H01L22/14 ,  H01L22/34 ,  H01L23/49827 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Kerf areas are located between the integrated circuit chips on a wafer. Via chain test structures are located in the kerf areas or test chips. The via chain test structures comprise a first conductor in a first area of the wafer. First via chains are connected at individual points to the first conductor. Each of the first via chains comprises an open-ended electrical circuit beginning at the first conductor and ending in an insulated region of a second area of the wafer. The via chain test structures comprise a second conductor in the second area. Second via chains are connected at individual points to the second conductor. Each of the second via chains comprises an open-ended electrical circuit beginning at the second conductor and ending in an insulated region of the first area.

Abstract translation: Kerf区域位于晶片上的集成电路芯片之间。 通过链条测试结构位于切口区域或测试芯片中。 通孔链测试结构包括在晶片的第一区域中的第一导体。 首先通过链条在各个点处连接到第一导体。 第一通孔链中的每一个包括从第一导体开始并在晶片的第二区域的绝缘区域结束的开放式电路。 通孔链测试结构包括第二区域中的第二导体。 第二通道链在各个点处连接到第二导体。 每个第二通孔链包括从第二导体开始并且终止于第一区域的绝缘区域的开放式电路。