公开(公告)号：US10103144B1

公开(公告)日：2018-10-16

申请号：US15799247

申请日：2017-10-31

Applicant: International Business Machines Corporation

Inventor： Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/762 ,  H01L21/82 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/165 ,  H01L29/16 ,  H01L29/51 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.

公开(公告)号：US20180129774A1

公开(公告)日：2018-05-10

申请号：US15862782

申请日：2018-01-05

Applicant: International Business Machines Corporation

Inventor： Stephen E. Greco ,  Rasit O. Topaloglu

IPC: G06F17/50 ,  G03F7/20

CPC classification number: G06F17/5081 ,  G03F7/70433 ,  G03F7/705 ,  G03F7/70633

Abstract: Various embodiments include computer-implemented methods, computer program products and systems for analyzing at least one feature in a layout representing an integrated circuit (IC) for an overlay effect. In some cases, approaches include a computer-implemented method including: modeling a topography of the IC by running at least one of a chemical mechanical polishing (CMP) model, a deposition model or an etch model on a data file representing the IC after formation of an uppermost layer; modeling the at least one feature in the IC for an overlay effect using the topography model of the IC; and modifying the data file representing the IC after formation of the uppermost layer in response to detecting the overlay effect in the at least one feature, the overlay effect occurring in a layer underlying the uppermost layer.

公开(公告)号：US09859208B1

公开(公告)日：2018-01-02

申请号：US15268604

申请日：2016-09-18

Applicant: International Business Machines Corporation

Inventor： Matthew S. Angyal ,  Naftali E. Lustig ,  Rasit O. Topaloglu

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76898 ,  H01L23/528

Abstract: A method for an interconnect structure including: forming a hard mask layer on a semiconductor substrate having a wiring line; patterning the hard mask layer to form a patterned hard mask layer having a hard mask layer opening; depositing a dielectric stack on the patterned hard mask layer and in the hard mask layer opening; patterning the dielectric stack to form a via opening aligned with the hard mask layer opening and to expose the wiring line through the via opening and the hard mask layer opening, a bottom of the via opening defined by the hard mask layer having the hard mask layer opening; and filling the via opening and the hard mask layer opening with a metal to form a via in contact with the wiring line.

公开(公告)号：US09710592B2

公开(公告)日：2017-07-18

申请号：US14883243

申请日：2015-10-14

Applicant: International Business Machines Corporation

Inventor： Stephen E. Greco ,  Vincent J. McGahay ,  Rasit O. Topaloglu

IPC: G06F17/00 ,  G06F17/50 ,  H01L21/768 ,  H01L21/67 ,  G03F7/20 ,  H01L21/311

CPC classification number: G06F17/5081 ,  G03F7/2022 ,  G06F17/5077 ,  H01L21/31144 ,  H01L21/67063 ,  H01L21/76802 ,  H01L21/76816

Abstract: A metal interconnect structure, a system and method of manufacture, wherein a design layout includes results in forming at least two trenches of different trench depths. The method uses a slightly modified BEOL processing stack to prevent metal interconnect structures from encroaching upon an underlying hard mask dielectric or metallic hard mask layer. Thus two trench depths are obtained by tuning parameters of the system and allowing areas exposed by two masks to have deeper trenches. Here, the BEOL Stack processing is modified to enable two trench depths by using a hardmask that defines the lowest etch depth. The design may be optimized by software which optimizes a design for electromigration (or setup timing violations) by utilizing secondary trench depths, checking space opportunity around wires, pushing wires out to generate space and converting a wire to deep trench wire.

公开(公告)号：US09424388B2

公开(公告)日：2016-08-23

申请号：US14573535

申请日：2014-12-17

Applicant: International Business Machines Corporation

Inventor： Stephen E. Greco ,  Rasit O. Topaloglu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F7/70066 ,  G03F7/705 ,  G03F7/70558 ,  G06F2217/12 ,  Y02P90/265

Abstract: In an approach to determine one or more exposure areas in a reticle field and associated lithography process parameters for the one or more exposure areas, a computer receives a semiconductor design and sends the semiconductor design to a design analysis program. Additionally, the computer receives data from the design analysis program. Furthermore, the computer determines the one or more exposure areas in the reticle field, and at least one lithography process parameter for each exposure area of the one or more exposure areas in the reticle field based, at least in part, on the data received from the design analysis program, the semiconductor design, and one or more clustering algorithms associated with the design analysis program.

Abstract translation: 在确定掩模版领域中的一个或多个曝光区域和用于一个或多个曝光区域的相关光刻工艺参数的方法中，计算机接收半导体设计并将半导体设计发送到设计分析程序。 此外，计算机从设计分析程序接收数据。 此外，计算机至少部分地基于从所述标线区域中接收的数据确定标线场中的一个或多个曝光区域以及至少一个光刻处理参数，所述至少一个光刻处理参数用于所述标线区域中的所述一个或多个曝光区域的每个曝光区域 设计分析程序，半导体设计以及与设计分析程序相关联的一个或多个聚类算法。

公开(公告)号：US09058457B2

公开(公告)日：2015-06-16

申请号：US14083578

申请日：2013-11-19

Applicant: International Business Machines Corporation

Inventor： Stephen E. Greco ,  Ian P. Stobert ,  Rasit O. Topaloglu

IPC: G06F17/50 ,  H01L21/66

CPC classification number: G06F17/5068 ,  G03F9/7026 ,  H01L22/12 ,  H01L22/20

Abstract: A method of determining focal planes during a photolithographic exposure of a wafer surface is provided. The method may include receiving data corresponding to a surface topography of the wafer surface and determining, based on the received data corresponding to the surface topography, a plurality of regions having substantially different topographies. Reticle design data is received for exposure on the wafer surface, whereby, from the received reticle design data, reticle design data subsets that are each allocated to a corresponding one of the determined plurality of regions are generated. A best fit focal plane is then generated for each of the determined plurality of regions.

Abstract translation: 提供了在晶片表面的光刻曝光期间确定焦平面的方法。 该方法可以包括接收对应于晶片表面的表面形貌的数据，并且基于与表面形貌对应的接收数据，确定具有基本上不同的拓扑图的多个区域。 接收掩模版设计数据以在晶片表面上曝光，由此，从接收到的掩模版设计数据生成分配给所确定的多个区域中的相应一个的掩模版设计数据子集。 然后为确定的多个区域中的每一个生成最佳拟合焦平面。

公开(公告)号：US08806393B1

公开(公告)日：2014-08-12

申请号：US13849764

申请日：2013-03-25

Applicant: International Business Machines Corporation

Inventor： Stephen E. Greco ,  Rasit O. Topaloglu

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: A design layout includes a conductive line level, at least one underlying conductive line level, and a via design level for vertically interconnecting structures in the conductive line level and the at least one underlying conductive line level. Stitch shapes are identified in the conductive line level. Test shapes are generated to determine whether vias formed in the area of the stitch shapes can extend to the at least one underlying conductive line level without contacting preexisting design shapes in the at least one underlying conductive line level structure and whether a new design shape can be inserted into the at least one underlying conductive line level with electrical isolation. As many new design shapes are inserted as possible to prevent extension of collateral via structures below the top surface of underlying metal line structures in a physical metal interconnect structure implementing the design layout.

Abstract translation: 设计布局包括导线级别，至少一个底层导电线电平以及用于在导线电平和至少一个底层导线电平线中垂直互连结构的通孔设计级别。 线迹形状在导线级别识别。 产生测试形状以确定在针迹形状的区域中形成的通孔是否可以延伸到至少一个下面的导电线水平，而不会接触至少一个下面的导电线水平结构中的预先存在的设计形状，以及新的设计形状是否可以 通过电气隔离插入至少一个底层导电线路。 尽可能插入许多新的设计形状，以防止通过实施设计布局的物理金属互连结构中下面的金属线结构的顶表面下方的结构延伸抵押物。

公开(公告)号：US11011415B2

公开(公告)日：2021-05-18

申请号：US16858484

申请日：2020-04-24

Applicant: International Business Machines Corporation

Inventor： Rasit O. Topaloglu ,  Naftali Lustig ,  Matthew Angyal

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: Multiple interconnect structures with reduced TDDB susceptibility and reduced stray capacitance are disclosed. The structures have one or more pairs of layers (an upper and a lower layer) that form layered pairs in the structure. In each of the upper and lower layers, dielectric material separates an upper pair of interconnects from a lower pair of interconnects or from other conductive material. Pairs of vias pass through the dielectric and mechanically and electrically connect the respective sides of the upper and lower sides of the interconnect. A gap of air separates all or part of the pair of vias and the electrical paths the vias are within. In alternative embodiments, the airgap may extend to the bottom of the vias, below the tops of the lower pair of interconnects, or deeper into the lower layer. Alternative process methods are disclosed for making the different embodiments of the structures.

公开(公告)号：US20200326911A1

公开(公告)日：2020-10-15

申请号：US16383879

申请日：2019-04-15

Applicant: International Business Machines Corporation

Inventor： Rasit O. Topaloglu ,  Jonathan Z. Sun ,  Matthias G. Gottwald ,  Chandrasekharan Kothandaraman

IPC: G06F7/58 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A true random number generator (TRNG) device having a magnetic tunnel junction (MTJ) structure coupled to a domain wall wire. The MTJ structure is formed of a free layer (FL) and a reference layer (RL) that sandwiches a tunnel barrier layer. The free layer has anisotropy energy sufficiently low to provide stochastic fluctuation in the orientation of the magnetic state of the free layer via thermal energy. The domain wall wire is coupled to the MTJ structure. The domain wall wire has a domain wall. Movement of the domain wall tunes a probability distribution of the fluctuation in the orientation of the magnetic state of the free layer. The domain wall can be moved by application of a suitable current through the wire to tune the probability distribution of 1's and 0's generated by a readout circuit the TRNG device.

公开(公告)号：US10804454B2

公开(公告)日：2020-10-13

申请号：US16597604

申请日：2019-10-09

Applicant: International Business Machines Corporation

Inventor： Jared Barney Hertzberg ,  Sami Rosenblatt ,  Rasit O. Topaloglu

IPC: H01L27/108 ,  H01L39/02 ,  H01L27/18 ,  G06N10/00 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L39/22 ,  H01L39/24 ,  H03K19/195

Abstract: A capacitive coupling device (superconducting C-coupler) includes a trench formed through a substrate, from a backside of the substrate, reaching a depth in the substrate, substantially orthogonal to a plane of fabrication on a frontside of the substrate, the depth being less than a thickness of the substrate. A superconducting material is deposited as a continuous conducting via layer in the trench with a space between surfaces of the via layer in the trench remaining accessible from the backside. A superconducting pad is formed on the frontside, the superconducting pad coupling with a quantum logic circuit element fabricated on the frontside. An extension of the via layer is formed on the backside. The extension couples to a quantum readout circuit element fabricated on the backside.