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    Self-aligned gate electrode diffusion barriers
    12.
    发明授权
    Self-aligned gate electrode diffusion barriers 有权
    自对准栅电极扩散阻挡层

    公开(公告)号：US08932920B2

    公开(公告)日：2015-01-13

    申请号：US13904060

    申请日：2013-05-29

    Applicant: International Business Machines Corporation

    Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Russell T. Herrin ,  Laura J. Schutz ,  Steven M. Shank

    IPC: H01L21/8238 ,  H01L27/092

    CPC classification number: H01L29/408 ,  H01L21/8238 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/092

    Abstract: A self-aligned diffusion barrier may be formed by forming a first masking layer, having a vertical sidewall on a semiconductor layer, above a first portion of the semiconductor layer. A first spacer layer, including a spacer region on the vertical sidewall, may be formed above the semiconductor layer. A second portion of the semiconductor layer not covered by the first masking layer or the spacer region may then be doped. A second masking layer may then be formed over the first spacer layer and planarized to expose at least a portion of the spacer region. The spacer region may then be etched to form a notch exposing a third portion of the semiconductor layer. The third portion may then be doped with a barrier dopant. The first masking layer may be removed and a second spacer layer filling the notch may be formed. The first portion may then be doped.

    Abstract translation: 可以通过在半导体层的第一部分上形成在半导体层上具有垂直侧壁的第一掩模层来形成自对准扩散势垒。 可以在半导体层上方形成包括垂直侧壁上的间隔区域的第一间隔层。 然后可以掺杂未被第一掩模层或间隔区域覆盖的半导体层的第二部分。 然后可以在第一间隔层上形成第二掩蔽层，并将其平坦化以暴露间隔区域的至少一部分。 然后可以蚀刻间隔区以形成露出半导体层的第三部分的凹口。 然后第三部分可以掺杂阻挡掺杂剂。 可以去除第一掩蔽层，并且可以形成填充凹口的第二间隔层。 然后可以掺杂第一部分。

    SELF-ALIGNED EMITTER-BASE IN ADVANCED BiCMOS TECHNOLOGY
    13.
    发明申请
    SELF-ALIGNED EMITTER-BASE IN ADVANCED BiCMOS TECHNOLOGY 有权
    自制BiCMOS技术中的自对准发射体

    公开(公告)号：US20140131773A1

    公开(公告)日：2014-05-15

    申请号：US14162256

    申请日：2014-01-23

    Applicant: International Business Machines Corporation

    Inventor： Kevin K. Chan ,  David L. Harame ,  Russell T. Herrin ,  Qizhi Liu

    IPC: H01L29/737

    CPC classification number: H01L29/737 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7371

    Abstract: A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, filling the respective slot.

    Abstract translation: 公开了一种自对准双极晶体管及其制造方法。 在一个实施例中，提供衬底和本征基极，随后是第一氧化物层，以及在第一氧化物层上的外部基极。 形成第一开口，暴露外部基底的表面的一部分。 在第一开口中形成侧壁间隔物，并且在外基的暴露表面上选择性地形成自对准氧化物掩模。 去除间隔物，并且使用自对准氧化物掩模，暴露的非本征基底和第一氧化物层被蚀刻以暴露本征基底层，形成第一和第二狭槽。 在第一和第二槽中的每一个中的暴露的固有和/或非本征基层上选择性地生长硅层条纹，填充相应的槽。

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