公开(公告)号：US09418846B1

公开(公告)日：2016-08-16

申请号：US14634050

申请日：2015-02-27

Applicant: International Business Machines Corporation

Inventor： Kevin K. Chan ,  Marinus J. P. Hopstaken ,  Young-Hee Kim ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Deborah A. Neumayer ,  Dae-Gyu Park ,  Uzma Rana ,  Tsong-Lin Tai

IPC: H01L21/02 ,  H01L29/207 ,  H01L21/225

CPC classification number: H01L21/242 ,  H01L21/2257 ,  H01L21/2258 ,  H01L21/28575 ,  H01L21/3228 ,  H01L21/3245 ,  H01L29/267 ,  H01L29/452 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78681

Abstract: An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Additionally, the approach includes performing a low temperature anneal in an oxygen free environment followed by depositing a metal layer on the dopant layer. Furthermore, the approach includes alloying the metal layer with the dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.

Abstract translation: 提供在半导体器件中形成掺杂剂结的方法的方法。 该方法包括对半导体层的暴露表面进行表面改性处理，并在半导体层的暴露表面上沉积掺杂剂材料。 另外，该方法包括在无氧环境中进行低温退火，然后在掺杂剂层上沉积金属层。 此外，该方法包括将金属层与掺杂剂层合金化以形成半导体器件结，其中半导体层由III-V族半导体材料组成，表面改性处理发生在真空室中以从暴露的表面去除表面氧化物 半导体层的表面，并且上述每个过程在低温下发生。

公开(公告)号：US20160172465A1

公开(公告)日：2016-06-16

申请号：US15047871

申请日：2016-02-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng-Wei Cheng ,  Edward W. Kiewra ,  Amlan Majumdar ,  Uzma Rana ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L29/66 ,  H01L29/201 ,  H01L29/20 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/66522 ,  H01L21/02488 ,  H01L21/02494 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78681

Abstract: A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.

公开(公告)号：US09287115B2

公开(公告)日：2016-03-15

申请号：US14206220

申请日：2014-03-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng-Wei Cheng ,  Edward W. Kiewra ,  Amlan Majumdar ,  Uzma Rana ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L21/02

CPC classification number: H01L29/66522 ,  H01L21/02488 ,  H01L21/02494 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78681

Abstract: A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.

Abstract translation: 一种在电介质材料上直接形成包括III-V族半导体材料的半导体衬底的方法，该电介质材料包括在电介质层中形成沟槽，并且在从沟槽的基底延伸到沟槽的暴露的上表面 包括衬底的底层半导体。 从半导体衬底的暴露的上表面延伸填充至少一部分沟槽形成III-V半导体材料。

公开(公告)号：US20150262818A1

公开(公告)日：2015-09-17

申请号：US14206220

申请日：2014-03-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng-Wei Cheng ,  Edward W. Kiewra ,  Amlan Majumdar ,  Uzma Rana ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66522 ,  H01L21/02488 ,  H01L21/02494 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78681

Abstract: A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.

Abstract translation: 一种在电介质材料上直接形成包括III-V族半导体材料的半导体衬底的方法，该电介质材料包括在电介质层中形成沟槽，并且在从沟槽的基底延伸到沟槽的暴露的上表面 包括衬底的底层半导体。 从半导体衬底的暴露的上表面延伸填充至少一部分沟槽形成III-V半导体材料。

公开(公告)号：US20150048423A1

公开(公告)日：2015-02-19

申请号：US14028639

申请日：2013-09-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robert L. Bruce ,  Cheng-Wei Cheng ,  Joel P. de Souza ,  Ryan M. Martin ,  Uzma Rana ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L29/267

CPC classification number: H01L21/02658 ,  H01L21/02381 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02642 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/267

Abstract: A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench.

Abstract translation: 在单个元件衬底上形成结晶化合物材料的方法包括在单一元件晶体衬底中蚀刻高纵横比沟槽，并在衬底上以及在沟槽的侧壁和底部上形成电介质层。 从沟槽的底部去除电介质以在沟槽的底部露出衬底。 选择性地在沟槽底部的衬底上生长结晶化合物材料。