公开(公告)号：US20160254150A1

公开(公告)日：2016-09-01

申请号：US14634050

申请日：2015-02-27

Applicant: International Business Machines Corporation

Inventor： Kevin K. Chan ,  Marinus J.P. Hopstaken ,  Young-Hee Kim ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Deborah A. Neumayer ,  Dae-Gyu Park ,  Uzma Rana ,  Tsong-Lin Tai

IPC: H01L21/02 ,  H01L21/225 ,  H01L29/207

CPC classification number: H01L21/242 ,  H01L21/2257 ,  H01L21/2258 ,  H01L21/28575 ,  H01L21/3228 ,  H01L21/3245 ,  H01L29/267 ,  H01L29/452 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78681

Abstract: An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Additionally, the approach includes performing a low temperature anneal in an oxygen free environment followed by depositing a metal layer on the dopant layer. Furthermore, the approach includes alloying the metal layer with the dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.

Abstract translation: 提供在半导体器件中形成掺杂剂结的方法的方法。 该方法包括对半导体层的暴露表面进行表面改性处理，并在半导体层的暴露表面上沉积掺杂剂材料。 此外，该方法包括在无氧环境中进行低温退火，然后在掺杂剂层上沉积金属层。 此外，该方法包括将金属层与掺杂剂层合金化以形成半导体器件结，其中半导体层由III-V族半导体材料组成，表面改性处理发生在真空室中以从暴露的表面去除表面氧化物 半导体层的表面，并且上述每个过程在低温下发生。

公开(公告)号：US20150048422A1

公开(公告)日：2015-02-19

申请号：US13968756

申请日：2013-08-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robert L. Bruce ,  Cheng-Wei Cheng ,  Joel P. de Souza ,  Ryan M. Martin ,  Uzma Rana ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L21/02 ,  H01L29/267

CPC classification number: H01L21/02658 ,  H01L21/02381 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02642 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/267

Abstract: A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench.

Abstract translation: 在单个元件衬底上形成结晶化合物材料的方法包括在单一元件晶体衬底中蚀刻高纵横比沟槽，并在衬底上以及在沟槽的侧壁和底部上形成电介质层。 从沟槽的底部去除电介质以在沟槽的底部露出衬底。 选择性地在沟槽底部的衬底上生长结晶化合物材料。

公开(公告)号：US20150030047A1

公开(公告)日：2015-01-29

申请号：US13949973

申请日：2013-07-24

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Frank R. Libsch ,  Tak H. Ning ,  Uzma Rana ,  Kuen-Ting Shiu

IPC: H01S5/026

CPC classification number: H01S5/2275 ,  H01S3/0637 ,  H01S3/2375 ,  H01S5/021 ,  H01S5/026 ,  H01S5/1017 ,  H01S5/1057 ,  H01S5/125 ,  H01S5/166 ,  H01S5/2018 ,  H01S5/3013 ,  H01S5/18363 ,  H01S3/0315

Abstract: III-V lasers integrated with silicon photonic circuits and methods for making the same include a three-layer semiconductor stack formed from III-V semiconductors on a substrate, where a middle layer has a lower bandgap than a top layer and a bottom layer; a mirror region monolithically formed at a first end of the stack, configured to reflect emitted light in the direction of the stack; and a waveguide region monolithically formed at a second end of the stack, configured to transmit emitted light.

Abstract translation: 与硅光子电路集成的III-V激光器及其制造方法包括由衬底上的III-V半导体形成的三层半导体叠层，其中中间层具有比顶层和底层更低的带隙; 整体地形成在所述堆叠的第一端处的反射镜区域，被构造成在所述堆叠的方向上反射发射的光; 以及波导区域，其单片地形成在所述堆叠的第二端处，被配置为透射发射的光。

公开(公告)号：US20240429277A1

公开(公告)日：2024-12-26

申请号：US18213493

申请日：2023-06-23

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Jingyun Zhang ,  Junli Wang ,  Chen Zhang ,  Uzma Rana

IPC: H01L29/06 ,  H01L25/07 ,  H01L25/18 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor structure including a plurality of stacked devices having different gate dielectrics is provided. The different gate dielectrics for the stacked devices are designed to improve the performance and the reliability for each of the stacked devices.

公开(公告)号：US09882021B2

公开(公告)日：2018-01-30

申请号：US15047871

申请日：2016-02-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng-Wei Cheng ,  Edward W. Kiewra ,  Amlan Majumdar ,  Uzma Rana ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/20 ,  H01L29/201 ,  H01L29/786

CPC classification number: H01L29/66522 ,  H01L21/02488 ,  H01L21/02494 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78681

Abstract: A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.

公开(公告)号：US20160329211A1

公开(公告)日：2016-11-10

申请号：US15211010

申请日：2016-07-15

Applicant: International Business Machines Corporation

Inventor： Kevin K. Chan ,  Marinus J.P. Hopstaken ,  Young-Hee Kim ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Deborah A. Neumayer ,  Dae-Gyu Park ,  Uzma Rana ,  Tsong-Lin Tai

IPC: H01L21/24 ,  H01L29/66 ,  H01L21/225 ,  H01L29/267 ,  H01L21/322 ,  H01L21/324

CPC classification number: H01L21/242 ,  H01L21/2257 ,  H01L21/2258 ,  H01L21/28575 ,  H01L21/3228 ,  H01L21/3245 ,  H01L29/267 ,  H01L29/452 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78681

Abstract: An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Furthermore, the approach includes alloying a metal layer with a dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.

Abstract translation: 提供在半导体器件中形成掺杂剂结的方法的方法。 该方法包括对半导体层的暴露表面进行表面改性处理，并在半导体层的暴露表面上沉积掺杂剂材料。 此外，该方法包括使金属层与掺杂剂层合金以形成半导体器件结，其中半导体层由III-V族半导体材料组成，表面改性处理发生在真空室中以从暴露的表面去除表面氧化物 半导体层的表面，并且上述每个过程在低温下发生。

公开(公告)号：US20140264607A1

公开(公告)日：2014-09-18

申请号：US13800398

申请日：2013-03-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anirban Basu ,  Cheng-Wei Cheng ,  Amlan Majumdar ,  Ryan M. Martin ,  Uzma Rana ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material.

公开(公告)号：US20150255281A1

公开(公告)日：2015-09-10

申请号：US14720427

申请日：2015-05-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robert L. Bruce ,  Cheng-Wei Cheng ,  Joel P. de Souza ,  Ryan M. Martin ,  Uzma Rana ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L21/02

CPC classification number: H01L21/02658 ,  H01L21/02381 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02642 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/267

Abstract: A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench.

Abstract translation: 在单个元件衬底上形成结晶化合物材料的方法包括在单一元件晶体衬底中蚀刻高纵横比沟槽，并在衬底上以及在沟槽的侧壁和底部上形成电介质层。 从沟槽的底部去除电介质以在沟槽的底部露出衬底。 选择性地在沟槽底部的衬底上生长结晶化合物材料。

公开(公告)号：US08937299B2

公开(公告)日：2015-01-20

申请号：US13967102

申请日：2013-08-14

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Cheng-Wei Cheng ,  Amlan Majumdar ,  Ryan M. Martin ,  Uzma Rana ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L29/78 ,  H01L29/267 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material.

Abstract translation: 一种用于形成鳍状场效应晶体管的方法，包括在硅衬底上形成电介质层，在电介质层中形成高达纵横比的沟槽直至衬底，高纵横比包括大于或等于1:1的高宽比;以及 使用纵横比捕获工艺在沟槽中外延生长含硅的半导体材料以形成翅片。 蚀刻一个或多个电介质层以暴露鳍片的一部分。 在翅片的一部分上外延生长阻挡层，在鳍片上方形成栅叠层。 围绕翅片和门叠层的部分形成间隔件。 将掺杂剂植入翅片的部分。 源极和漏极区域使用非含硅半导体材料生长在翅片上。

公开(公告)号：US09679775B2

公开(公告)日：2017-06-13

申请号：US15211010

申请日：2016-07-15

Applicant: International Business Machines Corporation

Inventor： Kevin K. Chan ,  Marinus J. P. Hopstaken ,  Young-Hee Kim ,  Masaharu Kobayashi ,  Effendi Leobandung ,  Deborah A. Neumayer ,  Dae-Gyu Park ,  Uzma Rana ,  Tsong-Lin Tai

IPC: H01L21/225 ,  H01L29/66 ,  H01L21/24 ,  H01L29/45 ,  H01L21/285 ,  H01L21/322 ,  H01L21/324 ,  H01L29/267 ,  H01L29/51

CPC classification number: H01L21/242 ,  H01L21/2257 ,  H01L21/2258 ,  H01L21/28575 ,  H01L21/3228 ,  H01L21/3245 ,  H01L29/267 ,  H01L29/452 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78681

Abstract: An approach to providing a method of forming a dopant junction in a semiconductor device. The approach includes performing a surface modification treatment on an exposed surface of a semiconductor layer and depositing a dopant material on the exposed surface of the semiconductor layer. Furthermore, the approach includes alloying a metal layer with a dopant layer to form a semiconductor device junction where the semiconductor layer is composed of a Group III-V semiconductor material, the surface modification treatment occurs in a vacuum chamber to remove surface oxides from the exposed surface of the semiconductor layer, and each of the above processes occur at a low temperature.