公开(公告)号：US20180197961A1

公开(公告)日：2018-07-12

申请号：US15917484

申请日：2018-03-09

Applicant: International Business Machines Corporation

Inventor： Kevin K. Chan ,  Cheng-Wei Cheng ,  Jack Oon Chu ,  Yanning Sun ,  Jeng-Bang Yau

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/45 ,  H01L29/201 ,  H01L29/20 ,  H01L29/08 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/285 ,  H01L21/283

CPC classification number: H01L29/41783 ,  H01L21/02546 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/32051 ,  H01L21/32134 ,  H01L29/0847 ,  H01L29/20 ,  H01L29/201 ,  H01L29/452 ,  H01L29/665 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7835

Abstract: A field effect transistor is provided which includes a plurality of fins, at least a portion of a given fin including a respective source region, and a raised source disposed at least partially on the fins and including III-V material. The field effect transistor further includes a diffusion barrier disposed at least partially on the raised source and including transition metal bonded with silicon or germanium, and a gate stack capacitively coupled at least to the respective source regions of the fins.

公开(公告)号：US20170125607A1

公开(公告)日：2017-05-04

申请号：US14931307

申请日：2015-11-03

Applicant: International Business Machines Corporation

Inventor： Bahman Hekmatshoartabari ,  Ghavam G. Shahidi ,  Yanning Sun

IPC: H01L29/808 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/417 ,  H01L27/12 ,  H01L29/04 ,  H01L29/423 ,  H01L21/283

CPC classification number: H01L29/802 ,  H01L21/283 ,  H01L27/12 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/1054 ,  H01L29/1066 ,  H01L29/1604 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/456 ,  H01L29/66901 ,  H01L29/66916 ,  H01L29/8086

Abstract: A junction field effect transistor (JFET) comprises an insulating carrier substrate, a base semiconductor substrate formed on the insulating carrier substrate and a gate region formed on the base semiconductor substrate. The gate region forms a junction with the base semiconductor substrate. The JFET further comprises a first source/drain region formed on the base semiconductor substrate and located on a first side of the gate region and a second source/drain region formed on the base semiconductor substrate and located on a second side of the gate region. A gate stack is deposited on the gate region, a first source/drain stack is deposited on the first source/drain region and a second source/drain stack is deposited on the second source/drain region. At least one of the gate stack, first source/drain stack and second source/drain stack overlaps onto another one of the gate stack, first source/drain stack and second source/drain stack.

公开(公告)号：US20170092763A1

公开(公告)日：2017-03-30

申请号：US15377722

申请日：2016-12-13

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Pranita Kerber ,  Effendi Leobandung ,  Amlan Majumdar ,  Renee T. Mo ,  Yanning Sun

IPC: H01L29/78 ,  H01L21/311 ,  H01L29/32 ,  H01L29/66 ,  H01L23/535 ,  H01L29/06

CPC classification number: H01L29/7835 ,  H01L21/2258 ,  H01L21/31105 ,  H01L21/31116 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/32 ,  H01L29/66462 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure containing a high mobility semiconductor channel material, i.e., a III-V semiconductor material, and asymmetrical source/drain regions located on the sidewalls of the high mobility semiconductor channel material is provided. The asymmetrical source/drain regions can aid in improving performance of the resultant device. The source region contains a source-side epitaxial doped semiconductor material, while the drain region contains a drain-side epitaxial doped semiconductor material and an underlying portion of the high mobility semiconductor channel material.

公开(公告)号：US20170092722A1

公开(公告)日：2017-03-30

申请号：US15135655

申请日：2016-04-22

Applicant: International Business Machines Corporation

Inventor： Kevin K. Chan ,  Cheng-Wei Cheng ,  Jack Oon Chu ,  Yanning Sun ,  Jeng-Bang Yau

IPC: H01L29/08 ,  H01L29/20 ,  H01L21/02 ,  H01L29/78 ,  H01L29/45 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/417 ,  H01L21/285

CPC classification number: H01L29/41783 ,  H01L21/02546 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/32051 ,  H01L21/32134 ,  H01L29/0847 ,  H01L29/20 ,  H01L29/201 ,  H01L29/452 ,  H01L29/665 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7835

Abstract: A method is presented for forming a diffusion barrier in a field effect transistor with a source. A raised source is formed at least partially on the source with the raised source comprising III-V material. An interfacial layer is formed at least partially on the raised source with the interfacial layer comprising silicon or germanium. A metal layer is formed at least partially on the interfacial layer with the metal layer comprising transition metal. The diffusion barrier is formed at least partially on the raised source with the diffusion barrier layer comprising transition metal from the metal layer bonded to silicon or germanium from the interfacial layer. Similar processing forms a corresponding diffusion barrier on a raised drain.

公开(公告)号：US20160254352A1

公开(公告)日：2016-09-01

申请号：US15146148

申请日：2016-05-04

Applicant: International Business Machines Corporation

Inventor： Cheng-Wei Cheng ,  Pranita Kerber ,  Young-Hee Kim ,  Effendi Leobandung ,  Yanning Sun

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L29/207 ,  H01L29/08 ,  H01L21/02

CPC classification number: H01L29/20 ,  H01L21/02392 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/0257 ,  H01L21/30612 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/8252 ,  H01L29/0603 ,  H01L29/0607 ,  H01L29/0657 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/12 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833

Abstract: A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the exposed extension region using a first in-situ dopant and epitaxially growing a source or drain on the halo layer using a second in-situ dopant, wherein the first in-situ dopant and the second in-situ dopant are of opposite doping polarity. Using an opposite doping polarity may provide an energy band barrier for the semiconductor device and reduce leakage current. A corresponding apparatus is also disclosed herein.

公开(公告)号：US20150325650A1

公开(公告)日：2015-11-12

申请号：US14793772

申请日：2015-07-08

Applicant: International Business Machines Corporation

Inventor： Anirban Basu ,  Amlan Majumdar ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/778

CPC classification number: H01L29/7787 ,  H01L21/02455 ,  H01L21/02538 ,  H01L21/28575 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/42316 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66462 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/778 ,  H01L29/7784

Abstract: A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.

公开(公告)号：US09087775B2

公开(公告)日：2015-07-21

申请号：US13760277

申请日：2013-02-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng-Wei Cheng ,  Jack O. Chu ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L29/66 ,  H01L29/267 ,  H01L29/772 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/267 ,  H01L21/02387 ,  H01L21/02439 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/02664 ,  H01L21/28575 ,  H01L21/3228 ,  H01L29/452 ,  H01L29/66522 ,  H01L29/772 ,  H01L29/78

Abstract: A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.

Abstract translation: 半导体结构包括III-V单晶层和锗表面层。 从III-V单晶层和锗表面层之间直接形成中间层，所述材料被选择为在中间层和锗表面层之间提供更强的成核结合，而不是直接在III-V单晶层和 锗表面层，使得提供连续的，相对缺陷的锗表面层。

公开(公告)号：US20150048422A1

公开(公告)日：2015-02-19

申请号：US13968756

申请日：2013-08-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robert L. Bruce ,  Cheng-Wei Cheng ,  Joel P. de Souza ,  Ryan M. Martin ,  Uzma Rana ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L21/02 ,  H01L29/267

CPC classification number: H01L21/02658 ,  H01L21/02381 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02642 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/267

Abstract: A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench.

Abstract translation: 在单个元件衬底上形成结晶化合物材料的方法包括在单一元件晶体衬底中蚀刻高纵横比沟槽，并在衬底上以及在沟槽的侧壁和底部上形成电介质层。 从沟槽的底部去除电介质以在沟槽的底部露出衬底。 选择性地在沟槽底部的衬底上生长结晶化合物材料。

公开(公告)号：US20150028388A1

公开(公告)日：2015-01-29

申请号：US13950788

申请日：2013-07-25

Applicant: International Business Machines Corporation

Inventor： Amlan Majumdar ,  Yanning Sun

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/0847 ,  H01L29/267 ,  H01L29/365 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7784 ,  H01L29/78 ,  H01L29/7848

Abstract: A structure and method for fabricating a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) with self-aligned and overlapped extensions using a replacement gate process is disclosed. The a III-V compound semiconductor-containing heterostructure field-effect transistor (FET) structure may be formed by forming a III-V compound semiconductor-containing heterostructure having multiple layers and a T-shaped gate structure using a gate replacement process. The T-shaped gate structure may be formed with a bottom surface substantially below an upper surface of the III-V compound semiconductor-containing heterostructure and an upper surface above the III-V compound semiconductor-containing heterostructure. An undoped region may be formed below the bottom surface of the T-shaped gate structure on a layer of the III-V compound semiconductor-containing heterostructure.

公开(公告)号：US10128343B2

公开(公告)日：2018-11-13

申请号：US15917484

申请日：2018-03-09

Applicant: International Business Machines Corporation

Inventor： Kevin K. Chan ,  Cheng-Wei Cheng ,  Jack Oon Chu ,  Yanning Sun ,  Jeng-Bang Yau

IPC: H01L29/41 ,  H01L29/08 ,  H01L29/20 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/283 ,  H01L29/201 ,  H01L21/285 ,  H01L21/02

Abstract: A field effect transistor is provided which includes a plurality of fins, at least a portion of a given fin including a respective source region, and a raised source disposed at least partially on the fins and including III-V material. The field effect transistor further includes a diffusion barrier disposed at least partially on the raised source and including transition metal bonded with silicon or germanium, and a gate stack capacitively coupled at least to the respective source regions of the fins.