公开(公告)号：US09324846B1

公开(公告)日：2016-04-26

申请号：US14591946

申请日：2015-01-08

Applicant: International Business Machines Corporation

Inventor： Renata A. Camillo-Castillo ,  Vibhor Jain ,  Marwan H. Khater ,  Santosh Sharma

IPC: H01L29/45 ,  H01L29/737 ,  H01L29/08 ,  H01L29/06 ,  H01L21/265 ,  H01L29/40 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/165 ,  H01L29/10

CPC classification number: H01L29/7371 ,  H01L21/26513 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/401 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/45 ,  H01L29/66242

Abstract: A method of forming a heterojunction bipolar transistor including a field plate. The method may include forming: a substrate having a selectively implanted collector (SIC) and a collector separated by a shallow trench isolation (STI), a field plate in the STI, the field plate extends below a top surface of the SIC, a base layer directly on the SIC, a heterojunction bipolar transistor (HBT) structure above the SIC, the HBT includes an emitter, the emitter is directly on the base layer, a fourth dielectric layer covering the HBT structure, the field plate and the collector, and an emitter contact, a field plate contact and a collector contact extending through the fourth dielectric layer, the emitter contact is in electrical connection with the emitter, the field plate contact is in electrical connection with the field plate and the collector contact is in electrical connection with the collector.

Abstract translation: 一种形成包括场板的异质结双极晶体管的方法。 该方法可以包括形成：具有选择性注入的集电极（SIC）的基板和通过浅沟槽隔离（STI）隔离的集电极，STI中的场板，场板延伸到SIC的顶表面下方， 直接在SIC上的SIC上的异质结双极晶体管（HBT）结构，HBT包括发射极，发射极直接在基极层上，覆盖HBT结构的第四电介质层，场板和集电极，以及 发射极接触，场板接触和延伸穿过第四介电层的集电极触点，发射极触点与发射极电连接，场板触点与场板电连接，并且集电极触点电连接 与收藏家。

公开(公告)号：US09070734B2

公开(公告)日：2015-06-30

申请号：US14528388

申请日：2014-10-30

Applicant: International Business Machines Corporation

Inventor： Renata Camillo-Castillo ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater

IPC: H01L29/66 ,  H01L27/082 ,  H01L21/331 ,  H01L29/737 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/737 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7371 ,  H01L29/7378

Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.

公开(公告)号：US20150053982A1

公开(公告)日：2015-02-26

申请号：US14528388

申请日：2014-10-30

Applicant: International Business Machines Corporation

Inventor： Renata Camillo-Castillo ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/737 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7371 ,  H01L29/7378

Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.

公开(公告)号：US08957456B1

公开(公告)日：2015-02-17

申请号：US13955382

申请日：2013-07-31

Applicant: International Business Machines Corporation

Inventor： Renata Camillo-Castillo ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater

IPC: H01L29/66 ,  H01L21/336 ,  H01L21/20 ,  H01L29/737 ,  G06F17/50

CPC classification number: H01L29/737 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7371 ,  H01L29/7378

Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.

Abstract translation: 异质结双极晶体管的制造方法，器件结构和设计结构。 在半导体衬底中形成沟槽隔离区和集电极。 收集器与沟槽隔离区域共同延伸。 形成第一半导体层，其包括设置在集电极和沟槽隔离区上的单晶部分。 形成第二半导体层，其包括设置在第一半导体层的单晶部分上并具有覆盖在沟槽隔离区域上的外边缘的单晶部分。 第一半导体层的截面具有大于集电体的第一宽度的第二宽度。 第二半导体层的截面具有大于第二宽度的第三宽度。 空腔从第二半导体层的截面的外边缘横向延伸到第一半导体层的部分。

公开(公告)号：US20150041956A1

公开(公告)日：2015-02-12

申请号：US14492582

申请日：2014-09-22

Applicant: International Business Machines Corporation

Inventor： Peng Cheng ,  Peter B. Gray ,  Vibhor Jain ,  Robert K. Leidy ,  Qizhi Liu

IPC: H01L29/732

CPC classification number: H01L29/732 ,  H01L21/76229 ,  H01L21/76283 ,  H01L29/66242 ,  H01L29/7378

Abstract: Device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures.

Abstract translation: 双极结型晶体管的器件结构和设计结构。 器件结构包括衬底中的集电极区域，延伸到衬底中并由电绝缘体构成的多个隔离结构以及衬底中的隔离区域。 隔离结构具有长度并且以横向于长度的间距布置，使得每个相邻的一对隔离结构被基板的相应部分分开。 隔离区域通过集电区域的第一部分与隔离结构中的至少一个横向分离。 隔离区域将收集区域的第二部分与收集器区域的第一部分横向分离。 器件结构还包括在集电极区域的第二部分上的本征基极和在本征基极上的发射极。 发射极相对于隔离结构的长度具有横向定向的长度。

公开(公告)号：US20140264341A1

公开(公告)日：2014-09-18

申请号：US13800091

申请日：2013-03-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Renata Camillo-Castillo ,  David L. Harame ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater

IPC: H01L29/73 ,  H01L29/66

CPC classification number: H01L29/7371 ,  H01L21/7624 ,  H01L21/8249 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/7325 ,  H01L2924/1305

Abstract: Fabrication methods, device structures, and design structures for a bipolar junction transistor. A dielectric structure is formed that is coextensive with a single crystal semiconductor material of a substrate in an active device region. A semiconductor layer is formed that includes a single crystal section coupled with the active device region. The semiconductor layer has an edge that overlaps with a top surface of the dielectric structure. An intrinsic base layer is formed on the semiconductor layer.

Abstract translation: 双极结晶体管的制造方法，器件结构和设计结构。 形成与有源器件区域中的衬底的单晶半导体材料共同延伸的电介质结构。 形成半导体层，其包括与有源器件区域耦合的单晶部分。 半导体层具有与电介质结构的顶表面重叠的边缘。 在半导体层上形成本征基层。

公开(公告)号：US10804364B2

公开(公告)日：2020-10-13

申请号：US16031371

申请日：2018-07-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/812 ,  H01L29/49 ,  H01L29/47 ,  H01L27/12 ,  H01L29/51

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

公开(公告)号：US10680074B2

公开(公告)日：2020-06-09

申请号：US15944018

申请日：2018-04-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Vibhor Jain ,  Qizhi Liu ,  John J. Pekarik

IPC: H01L21/28 ,  H01L27/12 ,  H01L29/47 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/812

Abstract: A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

公开(公告)号：US09588293B2

公开(公告)日：2017-03-07

申请号：US14749806

申请日：2015-06-25

Applicant: International Business Machines Corporation

Inventor： John J. Ellis-Monaghan ,  Brendan S. Harris ,  Vibhor Jain ,  Thomas Kessler ,  Yves T. Ngu ,  Sebastian T. Ventrone

IPC: G02B6/12 ,  G02B6/125 ,  G02B6/122 ,  G02B6/35 ,  G02B6/28 ,  B81B7/02

CPC classification number: G02B6/125 ,  B81B7/02 ,  B81B2201/045 ,  G02B6/1225 ,  G02B6/2808 ,  G02B6/3502 ,  G02B6/3562 ,  G02B6/357 ,  G02B6/3596 ,  G02B6/3598 ,  G02B2006/12145 ,  G02B2006/1215

Abstract: Various particular embodiments include a primary waveguide including an end section; cantilevered waveguides, each cantilevered waveguide including an end section disposed adjacent the end section of the primary waveguide; and control pins for applying an electrical bias to the cantilevered waveguides to selectively displace the end sections of the cantilevered waveguides away from the end section of the primary waveguide.

Abstract translation: 各种具体实施例包括：包括端部的主波导; 悬臂波导，每个悬臂式波导包括邻近初级波导的端部设置的端部; 以及控制引脚，用于将电偏压施加到悬臂波导，以选择性地使悬臂波导的端部远离主波导的端部。

公开(公告)号：US20150137185A1

公开(公告)日：2015-05-21

申请号：US14083769

申请日：2013-11-19

Applicant: International Business Machines Corporation

Inventor： Renata Camillo-Castillo ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater ,  Anthony K. Stamper

IPC: H01L29/737 ,  H01L29/66

CPC classification number: H01L29/7371 ,  H01L29/0649 ,  H01L29/66242

Abstract: Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A collector is formed in a semiconductor substrate, an intrinsic base is formed on the semiconductor substrate, and an extrinsic base is formed on the intrinsic base. An airgap is located vertically between the extrinsic base and the collector. A contact surface is located adjacent to the airgap. The contact surface is coupled with the collector. A spacer is located laterally between the airgap and the subcollector contact surface.

Abstract translation: 异质结双极晶体管的制造方法，器件结构和设计结构。 在半导体衬底中形成集电极，在半导体衬底上形成本征基极，在本征基底上形成非本征基极。 气隙垂直位于外部基极和收集器之间。 接触表面位于气隙附近。 接触表面与收集器结合。 间隔件横向位于气隙和子集电极接触表面之间。