利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

26 条记录 (耗时 0.045 秒)

    DUTY CYCLE CORRECTION CIRCUIT WITH REDUCED CURRENT CONSUMPTION
    14.
    发明申请
    DUTY CYCLE CORRECTION CIRCUIT WITH REDUCED CURRENT CONSUMPTION 失效
    具有降低电流消耗的占空比校正电路

    公开(公告)号：US20090206901A1

    公开(公告)日：2009-08-20

    申请号：US12333193

    申请日：2008-12-11

    申请人： Hee Woong Song ,  Yong Ju Kim ,  Sung Woo Han ,  Jae Min Jang ,  Hyung Soo Kim ,  Ji Wang Lee ,  Chang Kun Park ,  Ic Su Oh ,  Hae Rang Choi ,  Tae Jin Hwang

    发明人： Hee Woong Song ,  Yong Ju Kim ,  Sung Woo Han ,  Jae Min Jang ,  Hyung Soo Kim ,  Ji Wang Lee ,  Chang Kun Park ,  Ic Su Oh ,  Hae Rang Choi ,  Tae Jin Hwang

    IPC分类号： H03K5/04

    CPC分类号： H03K5/1565

    摘要： A duty cycle correction circuit includes a signal generating unit including a first signal generating unit coupled to a power supply voltage terminal and configured to output a complementary output signal of an output signal in response to a clock signal, and a second signal generating unit coupled to the power supply voltage terminal and configured to output the output signal in response to a complementary clock signal of the clock signal; a variable resistor unit coupled between the first and second signal generating units configured to vary an amount of current flowing into the signal generating unit according to a duty correction control signal, the duty correction control signal having a voltage level determined based on a voltage level of the output signal; and a current source coupled between the variable resistor unit and a ground voltage terminal configured to supply current to the signal generating unit.

    摘要翻译： 一种占空比校正电路包括：信号产生单元，包括耦合到电源电压端并被配置为响应于时钟信号输出输出信号的互补输出信号的第一信号产生单元，以及耦合到 所述电源电压端子被配置为响应于所述时钟信号的互补时钟信号而输出所述输出信号; 耦合在第一和第二信号发生单元之间的可变电阻器单元，被配置为根据占空比校正控制信号改变流入信号生成单元的电流量，该占空比校正控制信号具有基于电压电平 输出信号; 以及耦合在可变电阻器单元和被配置为向信号产生单元提供电流的接地电压端子之间的电流源。

    DELAY LOCKED LOOP CIRCUIT AND MEMORY DEVICE HAVING THE SAME
    19.
    发明申请
    DELAY LOCKED LOOP CIRCUIT AND MEMORY DEVICE HAVING THE SAME 有权
    延迟锁定环路电路和具有该环路的存储器件

    公开(公告)号：US20100090736A1

    公开(公告)日：2010-04-15

    申请号：US12346614

    申请日：2008-12-30

    申请人： Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang ,  Chang Kun Park

    发明人： Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang ,  Chang Kun Park

    IPC分类号： H03L7/08

    CPC分类号： H03L7/0814 ,  H03L7/07 ,  H03L7/0995 ,  H03L7/0998

    摘要： A DLL circuit includes a multiphase clock signal generating unit configured to produce a plurality of multiphase clock signals by delaying a reference clock signal for a unit delay time and to produce an enable signal that is enabled when one of the plurality of the multiphase clock signals synchronizes with the reference clock signal at a frequency, and a multiphase clock signal selecting unit configured to delay one of the plurality of the multiphase clock signals for a predetermined time in response to a first control signal, to compare a phase of a delayed multiphase clock signal with a phase of the reference clock signal, and to output one of the plurality of the multiphase clock signals as a delayed clock signal, wherein a phase of the delayed clock signal synchronizes with the phase of the reference clock signal when the enable signal is enabled.

    摘要翻译： 一个DLL电路包括一个多相时钟信号产生单元，被配置为通过延迟基准时钟信号来产生一个单位延迟时间来产生多个多相时钟信号，并产生一个使能信号，当多个多相时钟信号中的一个同步时 以及频率上的参考时钟信号，以及多相时钟信号选择单元，被配置为响应于第一控制信号而延迟多个多相时钟信号中的一个预定时间，以比较延迟的多相时钟信号的相位 具有参考时钟信号的相位，并且将多个多相时钟信号中的一个作为延迟的时钟信号输出，其中当使能信号被使能时，延迟的时钟信号的相位与参考时钟信号的相位同步 。