公开(公告)号：US08017930B2

公开(公告)日：2011-09-13

申请号：US11643438

申请日：2006-12-21

申请人： Jan Boris Philipp ,  Thomas Happ

发明人： Jan Boris Philipp ,  Thomas Happ

IPC分类号： H01L47/00

CPC分类号： H01L45/1675 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148

摘要： A memory cell includes a first electrode, a storage location, and a second electrode. The storage location includes a phase change material and contacts the first electrode. The storage location has a first cross-sectional width. The second electrode contacts the storage location and has a second cross-sectional width greater than the first cross-sectional width. The first electrode, the storage location, and the second electrode form a pillar phase change memory cell.

摘要翻译： 存储单元包括第一电极，存储位置和第二电极。 存储位置包括相变材料并与第一电极接触。 存储位置具有第一横截面宽度。 第二电极接触存储位置并且具有大于第一横截面宽度的第二横截面宽度。 第一电极，存储位置和第二电极形成柱状相变存储单元。

公开(公告)号：US07906368B2

公开(公告)日：2011-03-15

申请号：US11771501

申请日：2007-06-29

申请人： Matthew Breitwisch ,  Thomas Happ ,  Eric A. Joseph ,  Hsiang-Lan Lung ,  Jan Boris Philipp

发明人： Matthew Breitwisch ,  Thomas Happ ,  Eric A. Joseph ,  Hsiang-Lan Lung ,  Jan Boris Philipp

IPC分类号： H01L21/06

CPC分类号： H01L45/1675 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

摘要： An embodiment of the present invention includes a method of forming a nonvolatile phase change memory (PCM) cell. This method includes forming at least one bottom electrode; forming at least one phase change material layer on at least a portion of an upper surface of the bottom electrode; forming at least one heater layer on at least a portion of an upper surface of the phase change material layer; and shaping the heater layer into a tapered shape, such that an upper surface of the heater layer has a cross-sectional width that is longer than a cross-sectional width of a bottom surface of the heater layer contacting the phase change material layer.

摘要翻译： 本发明的实施例包括形成非易失性相变存储器（PCM）单元的方法。 该方法包括形成至少一个底部电极; 在所述底部电极的上表面的至少一部分上形成至少一个相变材料层; 在所述相变材料层的上表面的至少一部分上形成至少一个加热层; 并且将加热器层成形为锥形，使得加热器层的上表面的横截面宽度大于与相变材料层接触的加热器层的底表面的横截面宽度。

公开(公告)号：US07889536B2

公开(公告)日：2011-02-15

申请号：US11957878

申请日：2007-12-17

申请人： Thomas Happ ,  Jan Boris Philipp

发明人： Thomas Happ ,  Jan Boris Philipp

IPC分类号： G11C11/00 ,  G11C11/36

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/79

摘要： An integrated circuit includes a line, at least two quench devices coupled to the line, and a resistivity changing material memory cell coupled to the line. The at least two quench devices are configured to quench a write signal on the line during a write operation of the memory cell.

摘要翻译： 集成电路包括线路，耦合到线路的至少两个骤冷器件以及耦合到该线路的电阻率变化材料存储器单元。 至少两个骤冷装置被配置为在存储器单元的写入操作期间在线路上猝灭写入信号。

公开(公告)号：US07859894B2

公开(公告)日：2010-12-28

申请号：US11972415

申请日：2008-01-10

申请人： Thomas Happ ,  Zaidi Shoaib

发明人： Thomas Happ ,  Zaidi Shoaib

IPC分类号： G11C11/00

CPC分类号： G01K7/015 ,  G11C7/04 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

摘要： An integrated circuit that includes a plurality of phase-change memory cells, at least one write pulse generator, and at least one temperature sensor. The plurality of phase-change memory cells are each capable of defining at least a first and a second state. The write pulse generator generates a write pulse for the plurality of phase-change memory cells. The temperature sensor is capable of sensing temperature. The write pulse generator adjusts the write pulse for at least some of the phase-change memory cells in accordance with the temperature sensed by the temperature sensor.

摘要翻译： 一种集成电路，包括多个相变存储器单元，至少一个写入脉冲发生器和至少一个温度传感器。 多个相变存储单元各自能够至少限定第一状态和第二状态。 写脉冲发生器产生用于多个相变存储单元的写入脉冲。 温度传感器能感测温度。 写入脉冲发生器根据温度传感器感测的温度来调节至少一些相变存储器单元的写入脉冲。

公开(公告)号：US20100323493A1

公开(公告)日：2010-12-23

申请号：US12856007

申请日：2010-08-13

申请人： Jan Boris Philipp ,  Thomas Happ

发明人： Jan Boris Philipp ,  Thomas Happ

IPC分类号： H01L21/02

CPC分类号： H01L45/1683 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148

摘要： An integrated circuit is fabricated by providing a preprocessed wafer including a first electrode, depositing a dielectric material over the preprocessed wafer, etching an opening in the dielectric material to expose a portion of the first electrode and depositing a first resistivity changing material over exposed portions of the etched dielectric material and the first electrode. The first resistivity changing material is planarized to expose the etched dielectric material. A second resistivity changing material is deposited over the etched dielectric material and the first resistivity changing material, and an electrode material is deposited over the second resistivity changing material.

摘要翻译： 通过提供包括第一电极的预处理晶片，在预处理的晶片上沉积电介质材料，蚀刻介电材料中的开口以暴露第一电极的一部分并在第一电极的暴露部分上沉积第一电阻率变化材料来制造集成电路 蚀刻的电介质材料和第一电极。 第一电阻率变化材料被平坦化以暴露蚀刻的电介质材料。 第二电阻率变化材料沉积在蚀刻的电介质材料和第一电阻率变化材料上，并且电极材料沉积在第二电阻率变化材料上。

公开(公告)号：US07791933B2

公开(公告)日：2010-09-07

申请号：US11963119

申请日：2007-12-21

申请人： Mark Lamorey ,  Thomas Happ

发明人： Mark Lamorey ,  Thomas Happ

IPC分类号： G11C11/00

CPC分类号： G11C29/02 ,  G11C7/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0069 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50 ,  G11C2013/0078 ,  G11C2029/5006 ,  G11C2213/79

摘要： A system of writing data to a phase change random access memory (PCRAM) on an integrated circuit (IC), and a design structure including the IC embodied in a machine readable medium are disclosed. The system includes an array of phase change elements with a plurality of devices providing independent control of a row access and a column access to the PCRAM. A column line (bit line) is pre-charged to a single predetermined level prior to enabling current flow to a corresponding selected phase change element. A current flow in the phase change element with a row (word line) is initiated once the column (bit line) has been pre-charged, to write data to the PCRAM cell. The current flow is terminated in the phase change element by closing the column line (bit line) preferably by quenching.

摘要翻译： 公开了一种将数据写入集成电路（IC）上的相变随机存取存储器（PCRAM）的系统，以及包括体现在机器可读介质中的IC的设计结构。 该系统包括具有提供行访问的独立控制和对PCRAM的列访问的多个设备的相变元件阵列。 在使电流流动到相应的选定相变元件之前，列线（位线）被预充电到单个预定电平。 一旦列（位线）已预充电，就会启动具有行（字线）的相变元件中的电流，以将数据写入PCRAM单元。 通过优选通过淬火闭合列线（位线），在相变元件中终止电流。

公开(公告)号：US20100193763A1

公开(公告)日：2010-08-05

申请号：US12727672

申请日：2010-03-19

申请人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

发明人： Chieh-Fang Chen ,  Shih Hung Chen ,  Yi-Chou Chen ,  Thomas Happ ,  Chia Hua Ho ,  Ming-Hsiang Hsueh ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Jan Boris Philipp ,  Simone Raoux

IPC分类号： H01L45/00

CPC分类号： B82Y10/00 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/1273 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

摘要： A layer of nanoparticles having a dimension on the order of 10 nm is employed to form a current constricting layer or as a hardmask for forming a current constricting layer from an underlying insulator layer. The nanoparticles are preferably self-aligning and/or self-planarizing on the underlying surface. The current constricting layer may be formed within a bottom conductive plate, within a phase change material layer, within a top conductive plate, or within a tapered liner between a tapered via sidewall and a via plug contains either a phase change material or a top conductive material. The current density of the local structure around the current constricting layer is higher than the surrounding area, thus allowing local temperature to rise higher than surrounding material. The total current required to program the phase change memory device, and consequently the size of a programming transistor, is reduced due to the current constricting layer.

摘要翻译： 使用具有大约10nm的尺寸的纳米颗粒层形成电流收缩层或作为用于从下面的绝​​缘体层形成电流收缩层的硬掩模。 纳米颗粒优选在下面的表面上自对准和/或自平坦化。 电流收缩层可以形成在底部导电板内，在相变材料层内，在顶部导电板内，或在锥形衬垫之间的锥形衬里之间，锥形通孔侧壁和通孔插塞包含相变材料或顶部导电 材料。 电流收缩层周围的局部结构的电流密度高于周围区域，从而允许局部温度比周围材料高。 由于电流收缩层，减少编程相变存储器件所需的总电流以及编程晶体管的尺寸。

公开(公告)号：US07714315B2

公开(公告)日：2010-05-11

申请号：US11437211

申请日：2006-05-19

申请人： Thomas Happ ,  Jan Boris Philipp ,  Ulrike Gruening-von Schwerin

发明人： Thomas Happ ,  Jan Boris Philipp ,  Ulrike Gruening-von Schwerin

IPC分类号： H01L29/76

CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/128 ,  H01L45/1293 ,  H01L45/148

摘要： A memory includes an array of resistive memory cells, bit lines between rows of the memory cells for accessing the memory cells, and a conductive plate coupled to each of the memory cells.

摘要翻译： 存储器包括电阻存储器单元的阵列，用于存储单元的存储单元的行之间的位线以及耦合到每个存储单元的导电板。

公开(公告)号：US07696510B2

公开(公告)日：2010-04-13

申请号：US11948204

申请日：2007-11-30

申请人： Jan Boris Philipp ,  Thomas Happ

发明人： Jan Boris Philipp ,  Thomas Happ

IPC分类号： H01L47/00

CPC分类号： H01L27/2472 ,  Y10S438/90

摘要： An integrated circuit includes a first electrode, a second, a first resistivity changing material contacting the first electrode at a first interface, and a second resistivity changing material contacting the second electrode at a second interface. A direct communication path between the first interface and the second interface is greater than the lateral distance.

摘要翻译： 集成电路包括第一电极，第二电极，第一电阻率变化材料，在第一界面处接触第一电极，第二电阻率变化材料在第二界面处与第二电极接触。 第一接口和第二接口之间的直接通信路径大于横向距离。

公开(公告)号：US20100058018A1

公开(公告)日：2010-03-04

申请号：US12202581

申请日：2008-09-02

申请人： Michael Kund ,  Thomas Happ ,  GillYong Lee ,  Heinz Hoenigschmid ,  Rolf Weis ,  Christoph Ludwig

发明人： Michael Kund ,  Thomas Happ ,  GillYong Lee ,  Heinz Hoenigschmid ,  Rolf Weis ,  Christoph Ludwig

IPC分类号： G06F12/00

CPC分类号： G11C7/04 ,  G11C13/0002 ,  G11C13/0033 ,  G11C16/3431

摘要： An integrated circuit includes: a resistive memory having an array of resistive memory cells; a memory controller that controls operation of the resistive memory in accordance with external commands from an external device; and a memory scheduler coupled to the resistive memory and to the memory controller. The memory scheduler schedules internal maintenance operations within the resistive memory in response to trigger conditions indicated by at least one sensor signal or external command. The operation of the memory scheduler and performance of the internal maintenance operations are transparent to the external device and, optionally, transparent to the memory controller.

摘要翻译： 集成电路包括：具有电阻存储器单元阵列的电阻性存储器; 存储器控制器，其根据来自外部设备的外部命令来控制所述电阻性存储器的操作; 以及耦合到电阻存储器和存储器控制器的存储器调度器。 存储器调度器响应于由至少一个传感器信号或外部命令指示的触发条件来调度电阻性存储器内的内部维护操作。 存储器调度器的操作和内部维护操作的性能对于外部设备是透明的，并且可选地对存储器控制器是透明的。