公开(公告)号：US11569831B1

公开(公告)日：2023-01-31

申请号：US17656176

申请日：2022-03-23

Applicant: Infineon Technologies AG

Inventor： Luigi Grimaldi ,  Dmytro Cherniak ,  Qianqian Ha

IPC: H03M1/10 ,  H03L7/085 ,  H03L7/18 ,  G04F10/00 ,  H03L7/099 ,  H03M3/00

Abstract: A digital phase-locked loop (DPLL) may include a time-to-digital converter (TDC) to provide a phase error signal, a frequency-divider to perform frequency division on an output signal to generate a frequency-divided output signal, a delta-sigma-modulator (DSM) to provide a test signal that represents a quantization error of the DSM, and a digital-to-time converter (DTC) to at least partially remove the quantization error from the frequency-divided output signal based on the test signal to generate the feedback signal. The DPLL may include a circuit to cause the DTC to provide a percentage of the quantization error such that the percentage of the quantization error is in the phase error signal, and a TDC calibration component to calibrate the TDC by applying a gain adjustment factor to the TDC. The gain adjustment factor may be based on the test signal and the phase error signal including the percentage of the quantization error.

公开(公告)号：US11418205B1

公开(公告)日：2022-08-16

申请号：US17208761

申请日：2021-03-22

Applicant: Infineon Technologies AG

Inventor： Andreas Schwarz ,  Dmytro Cherniak ,  Luigi Grimaldi

IPC: H03D3/24 ,  H03L7/197 ,  H03L7/099 ,  H03L7/093

Abstract: In accordance with an embodiment, a method of operating a fractional-N phase locked loop (FN-PLL) includes: dividing a first clock signal using a multi-modulus divider (MMD) based on a modulus control signal to form a frequency-divided clock signal, where the first clock signal is based on an output clock of the PLL; generating the modulus control signal based on a divider control input value using a delta-sigma modulator (DSM); and when a fractional portion of the divider control input value is within a first range of values, and repeatedly removing a first number of clock cycles from the first clock signal before dividing the first clock signal using the MMD, where the first number of clock cycles is a non-integer number of clock cycles.

公开(公告)号：US11418199B1

公开(公告)日：2022-08-16

申请号：US17327049

申请日：2021-05-21

Applicant: Infineon Technologies AG ,  Politecnico Di Milano

Inventor： Dmytro Cherniak ,  Salvatore Levantino ,  Alessio Santiccioli

IPC: H03L7/087 ,  H03L7/099 ,  H04L7/033

Abstract: In accordance with an embodiment, a method of operating a phase locked loop (PLL), the method including: comparing a phase of a reference signal with a phase of a clock signal using a plurality of parallel matched phase detection circuits to provide a plurality of phase detection signals, where each of the plurality of the parallel matched phase detection circuits is configured to have a same phase difference to output characteristic; filtering a sum of the plurality of phase detection signals to form a filtered phase detection signal; and controlling a frequency of an oscillator using the filtered phase detection signal, where the oscillator is configured to provide the clock signal.

公开(公告)号：US11079415B2

公开(公告)日：2021-08-03

申请号：US16520978

申请日：2019-07-24

Applicant: Infineon Technologies AG

Inventor： Matteo Bassi ,  Giovanni Boi ,  Dmytro Cherniak ,  Fabio Padovan

IPC: H03L5/00 ,  H03B5/12 ,  G01R19/04

Abstract: A calibration circuit for calibrating a peak detector configured to detect a signal peak amplitude of an oscillator, including: a calibration oscillator configured to be supplied by at least two different supply voltages to generate respective calibration signals; a calibration peak detector configured to detect a calibration signal peak amplitude of each of the calibration signals; and a logic circuit configured to calibrate the peak detector based on the detected calibration signal peak amplitudes.

公开(公告)号：US20210036710A1

公开(公告)日：2021-02-04

申请号：US17073181

申请日：2020-10-16

Applicant: Infineon Technologies AG ,  Politecnico Di Milano

Inventor： Dmytro Cherniak ,  Salvatore Levantino ,  Marc Tiebout ,  Roberto Nonis

IPC: H03L7/24 ,  H03B5/12 ,  H03L7/197 ,  H03L7/093 ,  H03L7/099

Abstract: A phased-locked loop (PLL) circuit with an injection locked digital digitally controlled oscillator (ILD) that has an ILD control input element, an ILD injection input element and an ILD output element. The PLL circuit also includes an adaptive control unit (ACU), wherein the ACU is configured to receive an error signal and is configured to output an ILD control word. The ILD control input element is configured to receive the ILD control word, and the ILD control word may set a natural oscillation frequency of the ILD. The ILD is further configured to output a first output signal from the ILD output element, where the natural oscillation frequency may set a frequency of the first output signal.

公开(公告)号：US10855296B2

公开(公告)日：2020-12-01

申请号：US16585689

申请日：2019-09-27

Applicant: Infineon Technologies AG

Inventor： Matteo Bassi ,  Giovanni Boi ,  Dmytro Cherniak ,  Fabio Padovan

IPC: H03L7/24 ,  H03L7/18 ,  H03L7/099 ,  H03G5/14 ,  H03J5/24 ,  H03B5/12

Abstract: A circuit for calibrating an injection locked oscillator is provided. The injection locked oscillator includes an injection locking input, an LC tank and an oscillator output to output an oscillator output signal. The circuit is configured to adjust a capacitance of the LC tank to different values, detect an amplitude of the oscillator output signal for each value of the different values of the capacitance while an input signal having a target frequency is applied to the injection locking input, determine a maximum amplitude of the detected amplitudes, and select a value for operating the injection locked oscillator based on the determined maximum amplitude.

公开(公告)号：US20180241406A1

公开(公告)日：2018-08-23

申请号：US15438438

申请日：2017-02-21

Applicant: Infineon Technologies AG ,  Politecnico Di Milano

Inventor： Dmytro Cherniak ,  Salvatore Levantino ,  Marc Tiebout ,  Roberto Nonis

IPC: H03L7/24 ,  H03L7/099 ,  H03B5/12

CPC classification number: H03L7/24 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/124 ,  H03B2201/0208 ,  H03L7/0991

Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.

公开(公告)号：US12265146B2

公开(公告)日：2025-04-01

申请号：US18159413

申请日：2023-01-25

Applicant: Infineon Technologies AG

Inventor： Giovanni Boi ,  Fabio Padovan ,  Luigi Grimaldi ,  Dmytro Cherniak

IPC: G01R35/00 ,  G01R19/04

Abstract: A calibration circuit may include a calibration signal generator configured to receive an oscillator signal provided by an oscillator and generate a calibration signal based on the oscillator signal. The calibration signal may be generated to have a predetermined amplitude. The calibration circuit may include a calibration peak detector configured to detect a peak amplitude of the calibration signal. The calibration circuit may include a logic circuit configured to calibrate a peak detector connected to the oscillator based at least in part on the peak amplitude of the calibration signal.

公开(公告)号：US12149252B2

公开(公告)日：2024-11-19

申请号：US18064823

申请日：2022-12-12

Applicant: Infineon Technologies AG

Inventor： Luigi Grimaldi ,  Dmytro Cherniak ,  Fabio Padovan ,  Giovanni Boi

IPC: H03L7/081 ,  H03L7/107 ,  H03L7/23

Abstract: A digital phase-locked loop (DPLL) may include a delta-sigma modulator (DSM). The DSM may include a delay component configured to perform noise shaping of a quantization error introduced by the DSM. The DSM may include a noise transfer function (NTF) component configured to perform filtering of the quantization error introduced by the DSM. The DSM may include an adjustment transfer function (ATF) component configured to cause the filtering of the quantization error to be applied on top of the noise shaping such that an impact of the NTF component on the noise shaping is reduced.

公开(公告)号：US20220329206A1

公开(公告)日：2022-10-13

申请号：US17227755

申请日：2021-04-12

Applicant: Infineon Technologies AG

Inventor： David Seebacher ,  Matteo Bassi ,  Dmytro Cherniak ,  Fabio Padovan

IPC: H03F1/02 ,  H03F3/24

Abstract: In accordance with an embodiment, a method for operating a millimeter-wave power amplifier including an input transistor having an output node coupled to a load path of a cascode transistor includes: receiving a millimeter-wave transmit signal at a control node of the input transistor; amplifying the millimeter-wave transmit signal to form an output signal; providing the output signal to a load coupled to an output node of the cascode transistor; and adjusting a first DC bias current of the input transistor to form a substantially constant second DC bias current of the cascode transistor.