公开(公告)号：US20240355745A1

公开(公告)日：2024-10-24

申请号：US18759008

申请日：2024-06-28

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Zhiguo QIAN ,  Jianyong XIE

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H01L25/075 ,  H01L25/16

CPC classification number: H01L23/5381 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/0753 ,  H01L25/167 ,  H01L2224/81 ,  H01L2924/181

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US20230100576A1

公开(公告)日：2023-03-30

申请号：US17478450

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Srinivas V. PIETAMBARAM ,  Jianyong XIE ,  Krishna Vasanth VALAVALA

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/42

Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques directed to bridges having a glass core, where the bridges may include one or more thick traces and one or more thin traces, where the thin traces are layered closer to a surface of the glass core, and the thick traces are layered further away from the glass core. During operation, the thin traces may be used to transmit signals between the coupled dies, and the thick traces may be used to transmit power between the coupled dies. During manufacture, the rigidity and highly planner surface of the glass core may enable thinner traces closer to the surface of the glass core to be placed with greater precision resulting in increased overall quality and robustness of transmitted signals. Other embodiments may be described and/or claimed.

公开(公告)号：US20220093516A1

公开(公告)日：2022-03-24

申请号：US17540141

申请日：2021-12-01

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Zhiguo QIAN ,  Jianyong XIE

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US20200343202A1

公开(公告)日：2020-10-29

申请号：US16393047

申请日：2019-04-24

Applicant: Intel Corporation

Inventor： Lijiang WANG ,  Jianyong XIE ,  Arghya SAIN ,  Xiaohong JIANG ,  Sujit SHARAN ,  Kemal AYGUN

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/498

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first trace embedded in a package substrate. In an embodiment, the first trace comprises a first region, where the first region has a first width, and a second region, where the second region has a second width that is smaller than the first width.

公开(公告)号：US20200051916A1

公开(公告)日：2020-02-13

申请号：US16658866

申请日：2019-10-21

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Debendra MALLIK ,  Mathew J. MANUSHAROW ,  Jianyong XIE

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L21/48 ,  H01L23/00

Abstract: An embedded multi-die interconnect bridge (EMIB) die is configured with power delivery to the center of the EMIB die and the power is distributed to two dice that are interconnected across the EMIB die.

公开(公告)号：US20240321785A1

公开(公告)日：2024-09-26

申请号：US18734746

申请日：2024-06-05

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Sujit SHARAN ,  Jianyong XIE

IPC: H01L23/66 ,  H01L21/48 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L25/00 ,  H01L25/16

CPC classification number: H01L23/66 ,  H01L21/4846 ,  H01L23/5223 ,  H01L23/5286 ,  H01L23/5381 ,  H01L23/5389 ,  H01L25/16 ,  H01L25/50 ,  H01L23/481 ,  H01L2223/6666 ,  H01L2223/6672

Abstract: A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

公开(公告)号：US20230238332A1

公开(公告)日：2023-07-27

申请号：US18128960

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Zhiguo QIAN ,  Jianyong XIE

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/532 ,  H01L21/48 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L23/5381 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/13 ,  H01L23/53295 ,  H01L24/81 ,  H01L23/49816 ,  H01L24/16 ,  H01L23/49822 ,  H01L21/4846 ,  H01L23/3128 ,  H01L21/486 ,  H01L23/5226 ,  H01L24/17 ,  H01L2224/81

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.

公开(公告)号：US20200381350A1

公开(公告)日：2020-12-03

申请号：US16636620

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Sujit SHARAN ,  Kemal AYGUN ,  Zhiguo QIAN ,  Yidnekachew MEKONNEN ,  Zhichao ZHANG ,  Jianyong XIE

IPC: H01L23/498 ,  H01L23/00

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, wherein the die comprises a plurality of high density features. An interconnect bridge is embedded in the substrate, wherein the interconnect bridge may comprise a first region disposed on a surface of the interconnect bridge comprising a first plurality of features, wherein the first plurality of features comprises a first pitch. A second region disposed on the surface of the interconnect bridge comprises a second plurality of features comprising a second pitch, wherein the second pitch is greater than the first pitch.

公开(公告)号：US20200373235A1

公开(公告)日：2020-11-26

申请号：US16419374

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Andrew COLLINS ,  Sujit SHARAN ,  Jianyong XIE

IPC: H01L23/522 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L21/768

Abstract: Embodiments herein relate to systems, apparatuses, or processes for an interconnect hub for dies that includes a first side and a second side opposite the first side to couple with three or more dies, where the second side includes a plurality of electrical couplings to electrically couple at least one of the three or more dies to another of the three or more dies to facilitate data transfer between at least a subset of the three or more dies. The three or more dies may be tiled dies.

公开(公告)号：US20200235053A1

公开(公告)日：2020-07-23

申请号：US16634864

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Kemal AYGUN ,  Zhiguo QIAN ,  Jianyong XIE

IPC: H01L23/538 ,  H01L21/48

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a die disposed on a surface of a substrate, an interconnect bridge embedded in the substrate, and at least one vertical interconnect structure disposed through a portion of the interconnect bridge, wherein the at least one vertical interconnect structure is electrically and physically coupled to the die.