公开(公告)号：US20240071917A1

公开(公告)日：2024-02-29

申请号：US18384582

申请日：2023-10-27

Applicant: Intel Corporation

Inventor： Richard E. SCHENKER ,  Robert L. BRISTOL ,  Kevin L. LIN ,  Florian GSTREIN ,  James M. BLACKWELL ,  Marie KRYSAK ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Curtis W. WARD ,  Swaminathan SIVAKUMAR ,  Elliot N. TAN

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L27/0886 ,  H01L29/7848

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US20200066629A1

公开(公告)日：2020-02-27

申请号：US16346873

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Richard E. SCHENKER ,  Robert L. BRISTOL ,  Kevin L. LIN ,  Florian GSTREIN ,  James M. BLACKWELL ,  Marie KRYSAK ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Curtis W. WARD ,  Swaminathan SIVAKUMAR ,  Elliot N. TAN

IPC: H01L23/528 ,  H01L27/088 ,  H01L23/532 ,  H01L29/78 ,  H01L23/522

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US20200058548A1

公开(公告)日：2020-02-20

申请号：US16347507

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Eungnak HAN ,  Rami HOURANI ,  Florian GSTREIN ,  Gurpreet SINGH ,  Scott B. CLENDENNING ,  Kevin L. LIN ,  Manish CHANDHOK

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L23/522

Abstract: Selective hardmask-based approaches for conductive via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. The plurality of conductive lines includes alternating non-recessed conductive lines and recessed conductive lines. The non-recessed conductive lines are substantially co-planar with the ILD layer, and the recessed conductive lines are recessed relative to an uppermost surface of the ILD layer. A dielectric capping layer is in recess regions above the recessed conductive lines. A hardmask layer is over the non-recessed conductive lines but not over the dielectric capping layer of the recessed conductive lines. The hardmask layer differs in composition from the dielectric capping layer. A conductive via is in an opening in the dielectric capping layer and on one of the recessed conductive lines. A portion of the conductive via is on a portion of the hardmask layer.

公开(公告)号：US20190244806A1

公开(公告)日：2019-08-08

申请号：US16343385

申请日：2016-12-02

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  Kevin L. LIN ,  James M. BLACKWELL

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/768

Abstract: Surface-aligned lithographic patterning approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, an integrated circuit structure includes a substrate. A plurality of alternating first and second conductive lines is along a first direction of a back end of line (BEOL) metallization layer in a first inter-layer dielectric (ILD) layer above the substrate. A conductive via is on and electrically coupled to one of the conductive lines of the plurality of alternating first and second conductive lines, the conductive via centered over the one of the conductive lines. A second ILD layer is above plurality of alternating first and second conductive lines and laterally adjacent to the conductive via. The second ILD layer has an uppermost surface substantially co-planar with the flat top surface of the conductive via.

公开(公告)号：US20190165270A1

公开(公告)日：2019-05-30

申请号：US16320789

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Kevin L. LIN ,  Sarah E. ATANASOV ,  Kevin P. O'BRIEN ,  Robert L. BRISTOL

IPC: H01L45/00 ,  H01L27/24

Abstract: Spacer-based patterning for tight-pitch and low-variability random access memory (RAM) bit cells, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate having a top layer. An array of non-volatile random access memory (RAM) bit cells is disposed on the top layer of the substrate. The array of non-volatile RAM bit cells includes columns of non-volatile RAM bit cells along a first direction and rows of non-volatile RAM bit cells along a second direction orthogonal to the first direction. A plurality of recesses is in the top layer of the substrate, along the first direction between columns of the array of non-volatile RAM bit cells.

公开(公告)号：US20190146335A1

公开(公告)日：2019-05-16

申请号：US16097960

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： James M. BLACKWELL ,  Robert L. BRISTOL ,  Marie KRYSAK ,  Florian GSTREIN ,  Eungnak HAN ,  Kevin L. LIN ,  Rami HOURANI ,  Shane M. HARLSON

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/768 ,  G03F7/40

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

公开(公告)号：US20190139887A1

公开(公告)日：2019-05-09

申请号：US16096272

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Kevin L. LIN ,  Richard E. SCHENKER ,  Jeffery D. BIELEFELD ,  Rami HOURANI ,  Manish CHANDHOK

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate. A plurality of alternating first and second conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate. A dielectric layer is disposed on an uppermost surface of the first conductive line types but not along sidewalls of the first conductive line types, and is disposed along sidewalls of the second conductive line types but not on an uppermost surface of the second conductive line types.

公开(公告)号：US20190035677A1

公开(公告)日：2019-01-31

申请号：US16070172

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Richard E. SCHENKER ,  Hui Jae YOO ,  Kevin L. LIN ,  Jasmeet S. CHAWLA ,  Stephanie A. BOJARSKI ,  Satyarth SURI ,  Colin T. CARVER ,  Sudipto NASKAR

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/0337 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76865 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53271

Abstract: A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.