公开(公告)号：US20180165065A1

公开(公告)日：2018-06-14

申请号：US15575334

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Charles C. KUO ,  Justin S. BROCKMAN ,  Juan G. ALZATE VINASCO ,  Kaan OGUZ ,  Kevin P. O'BRIEN ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Satyarth SURI ,  Robert S. CHAU ,  Prashant MAJHI ,  Ravi PILLARISETTY ,  Elijah V. KARPOV

IPC: G06F7/58 ,  H01L43/08 ,  H01L43/02

CPC classification number: G06F7/588 ,  H01L43/02 ,  H01L43/08

Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) device with out-of-plane magnetizations for its free and fixed magnetic layers, and configured to have a magnetization offset away from a center and closer to a switching threshold of the MTJ device; and logic for generating random numbers according to a resistive state of the MTJ device.

公开(公告)号：US20200066967A1

公开(公告)日：2020-02-27

申请号：US16068078

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Satyarth SURI ,  Tejaswi K. INDUKURI ,  Robert B. TURKOT, JR. ,  James S. CLARKE

IPC: H01L43/02 ,  G11C11/16 ,  H01L43/12 ,  H01L27/22

Abstract: Damascene-based approaches for fabricating a pedestal for a magnetic tunnel junction (MTJ) device, and the resulting structures, are described. In an example, a magnetic tunnel junction (MTJ) device includes a metal line disposed in a dielectric layer disposed above a substrate, the metal line recessed below an uppermost surface of the dielectric layer. The MTJ device also includes a conductive pedestal disposed on the metal line and laterally adjacent to the dielectric layer. The MTJ device also includes a magnetic tunnel junction (MTJ) stack disposed on the conductive pedestal.

公开(公告)号：US20190035677A1

公开(公告)日：2019-01-31

申请号：US16070172

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Richard E. SCHENKER ,  Hui Jae YOO ,  Kevin L. LIN ,  Jasmeet S. CHAWLA ,  Stephanie A. BOJARSKI ,  Satyarth SURI ,  Colin T. CARVER ,  Sudipto NASKAR

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/0337 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/7682 ,  H01L21/76843 ,  H01L21/76847 ,  H01L21/76865 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76889 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53271

Abstract: A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.

公开(公告)号：US20190027537A1

公开(公告)日：2019-01-24

申请号：US16069165

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Christopher J. WIEGAND ,  Oleg GOLONZKA ,  MD Tofizur RAHMAN ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Kevin P. O'BRIEN ,  Kaan OGUZ ,  Tahir GHANI ,  Satyarth SURI

IPC: H01L27/22 ,  H01F10/32 ,  G11C11/16 ,  H01L23/528 ,  H01L43/02 ,  H01L23/532 ,  H01L43/12 ,  H01L21/768 ,  H01F41/32

CPC classification number: H01L27/228 ,  G11C11/161 ,  H01F10/3254 ,  H01F10/329 ,  H01F41/32 ,  H01L21/0273 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53238 ,  H01L27/226 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of dielectric layer above a substrates, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.

公开(公告)号：US20180248116A1

公开(公告)日：2018-08-30

申请号：US15753468

申请日：2015-09-18

Applicant: Intel Corporation

Inventor： Mark L. DOCZY ,  Brian S. DOYLE ,  Charles C. KUO ,  Kaan OGUZ ,  Kevin P. O'BRIEN ,  Satyarth SURI ,  Tejaswi K. INDUKURI

IPC: H01L43/12 ,  H01F10/32 ,  H01L43/08 ,  G11C11/16 ,  H01F41/34 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/329 ,  H01F41/34 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for removing a re-deposited layer and/or interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.

公开(公告)号：US20170345476A1

公开(公告)日：2017-11-30

申请号：US15503359

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Mark L. DOCZY ,  Kaan OGUZ ,  Brian S. DOYLE ,  Charles C. KUO ,  Robert S. CHAU ,  Satyarth SURI

IPC: G11C11/16 ,  H01L43/10 ,  H01L27/22 ,  H01L43/12 ,  H01F10/32

CPC classification number: G11C11/161 ,  H01F10/3286 ,  H01L27/222 ,  H01L43/10 ,  H01L43/12

Abstract: A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.

公开(公告)号：US20170271578A1

公开(公告)日：2017-09-21

申请号：US15503357

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Kevin P. O'BRIEN ,  Brian S. DOYLE ,  Kaan OGUZ ,  Robert S. CHAU ,  Satyarth SURI

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L43/08 ,  H01L43/10

Abstract: A method including forming a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a fully-crystalline sacrificial film or substrate including a crystal lattice similar to the crystal lattice of the dielectric material; and transferring the device stack from the sacrificial film to a device substrate. An apparatus including a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a device substrate wherein the fixed magnetic layer and the free magnetic layer each have a crystalline lattice conforming to a crystalline lattice of the sacrificial film or substrate on which they were formed prior to transfer to the device substrate.