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公开(公告)号：US20200211231A1
公开(公告)日：2020-07-02
申请号：US16235672
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： CARSON BROWNLEE , CARSTEN BENTHIN , JOSHUA BARCZAK , KAI XIAO , MICHAEL APODACA , PRASOONKUMAR SURTI , THOMAS RAOUX
Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.
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公开(公告)号：US20200175643A1
公开(公告)日：2020-06-04
申请号：US16208715
申请日：2018-12-04
Applicant: Intel Corporation
Inventor： TRAVIS SCHLUESSLER , ZACK WATERS , MICHAEL APODACA , JASON SURPRISE , PETER DOYLE
Abstract: Embodiments described herein provide data processing device comprising a processor, a memory, and a large draw monitor comprising a processing unit to determine whether a vertex count for a graphics workload exceeds a threshold value, and in response to a determination that the vertex count for the graphics workload exceeds the threshold value, to divide the graphics workload over graphics processing units instantiated on multiple separate tiles. Other embodiments may be described and claimed.
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13.发明申请FACILITATING EFFICIENT GRAPHICS COMMAND GENERATION AND EXECUTION FOR IMPROVED GRAPHICS PERFORMANCE AT COMPUTING DEVICES 有权促进有效图形在计算机设备上改进图形性能的命令生成和执行公开(公告)号：US20160364829A1
公开(公告)日：2016-12-15
申请号：US14738703
申请日：2015-06-12
Applicant: INTEL CORPORATION
Inventor： MICHAEL APODACA , DAVID M. CIMINI
IPC: G06T1/20
Abstract: A mechanism is described for facilitating efficient graphics command generation and execution for improved graphics performance at computing devices. A method of embodiments, as described herein, includes detecting an application programming interface (API) call to perform a plurality of transactions, where the API call is issued by an application at a first command buffer, where the plurality of transactions include a first set of transactions and a second set of transactions. The method may further include creating a second command buffer and appending the second command buffer to the first command buffer, where creating further includes separating the first set transactions from the second set of transactions. The method may further include executing, via the second command buffer, the first set of transactions, prior to executing the first set of transactions.
Abstract translation: 描述了一种机制，用于促进有效的图形命令生成和执行，以提高计算设备的图形性能。 如本文所述的实施例的方法包括检测应用程序编程接口（API）调用以执行多个事务，其中API调用由第一命令缓冲器处的应用程序发出，其中多个事务包括第一组 的交易和第二套交易。 该方法还可以包括创建第二命令缓冲器并将第二命令缓冲器附加到第一命令缓冲器，其中创建还包括将第一集合事务与第二组事务分离。 该方法还可以包括在执行第一组事务之前经由第二命令缓冲器执行第一组事务。
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14.发明公开公开(公告)号：US20230421738A1
公开(公告)日：2023-12-28
申请号：US18347278
申请日：2023-07-05
Applicant: Intel Corporation
Inventor： MAYURESH VARERKAR , STANLEY BARAN , MICHAEL APODACA , PRASOONKUMAR SURTI , ATSUO KUWAHARA , NARAYAN BISWAL , JILL BOYCE , YI-JEN CHIU , GOKCEN CILINGIR , BARNAN DAS , ATUL DIVEKAR , SRIKANTH POTLURI , NILESH SHAH , ARCHIE SHARMA
IPC: H04N13/111 , H04N19/597 , G06F9/38 , G06F3/01 , G06N20/00
CPC classification number: H04N13/111 , H04N19/597 , G06F9/3877 , G06F3/012 , G06N20/00
Abstract: A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.
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公开(公告)号：US20210272349A1
公开(公告)日：2021-09-02
申请号：US17306769
申请日：2021-05-03
Applicant: Intel Corporation
Inventor： TRAVIS SCHLUESSLER , ZACK WATERS , MICHAEL APODACA , DANIEL JOHNSTON , JASON SURPRISE , PRASOONKUMAR SURTI , SUBRAMANIAM MAIYURAN , PETER DOYLE , SAURABH SHARMA , ANKUR SHAH , MURALI RAMADOSS
Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.
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Patent Agency Ranking
公开(公告)号：US20210263853A1
公开(公告)日：2021-08-26
申请号：US16802427
申请日：2020-02-26
Applicant: Intel Corporation
Inventor： ZACK S. WATERS , TRAVIS SCHLUESSLER , MICHAEL APODACA , ANKUR SHAH
IPC: G06F12/0882 , G06F12/0837 , G06F12/1045 , G06F12/06 , G06F9/50 , G06F9/4401 , G06F9/54 , G06F11/30
Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.
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公开(公告)号：US20200211260A1
公开(公告)日：2020-07-02
申请号：US16235583
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： KAI XIAO , MICHAEL APODACA , CARSON BROWNLEE , THOMAS RAOUX , JOSHUA BARCZAK , GABOR LIKTOR
Abstract: Apparatus and method for bottom-up BVH refit. For example, one embodiment of an apparatus comprises: a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes; traversal hardware logic to traverse one or more rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node unit comprising circuitry and/or logic to perform refit operations on nodes of the hierarchical acceleration data structure, the refit operations to adjust spatial dimensions of one or more of the nodes; and an early termination evaluator to determine whether to proceed with refit operations or to terminate refit operations for a current node based on refit data associated with one or more child nodes of the current node.
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18.发明申请公开(公告)号：US20170140572A1
公开(公告)日：2017-05-18
申请号：US14941110
申请日：2015-11-13
Applicant: INTEL CORPORATION
Inventor： MICHAEL APODACA , SIDDHARTH Y. DHARMADHIKARI
CPC classification number: G06T1/20 , G06F9/00 , G06F9/30149 , G06F9/3877 , G09G5/363
Abstract: A mechanism is described for facilitating efficient processing of graphics commands at computing devices. A method of embodiments, as described herein, includes detecting a current object representing a bundled state of graphics commands in a command list to be processed at a graphics processor of a computing device, and evaluating the current object to determine a previous object bound to a first set of the graphics commands, where the first set of the graphics commands is associated with a first command state corresponding to the previous object. The method may further include copying a second set of the graphics commands to a command buffer associated with the command list, where the second set of the graphics commands represents a remainder of the graphics commands in the command list upon excluding the first set of the graphics commands. The method may further include facilitating the graphics processor to execute the second set of the graphics commands from the command buffer.
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公开(公告)号：US20230377209A1
公开(公告)日：2023-11-23
申请号：US18322194
申请日：2023-05-23
Applicant: Intel Corporation
Inventor： ABHISHEK R. APPU , PRASOONKUMAR SURTI , JILL BOYCE , SUBRAMANIAM MAIYURAN , MICHAEL APODACA , ADAM T. LAKE , JAMES HOLLAND , VASANTH RANGANATHAN , ALTUG KOKER , LIDONG XU , NIKOS KABURLASOS
CPC classification number: G06T9/002 , G06T9/007 , G06T15/005 , G06T9/008 , G06N3/045
Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.
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公开(公告)号：US20220366630A1
公开(公告)日：2022-11-17
申请号：US17876358
申请日：2022-07-28
Applicant: Intel Corporation
Inventor： TRAVIS SCHLUESSLER , ZACK WATERS , MICHAEL APODACA , DANIEL JOHNSTON , JASON SURPRISE , PRASOONKUMAR SURTI , SUBRAMANIAM MAIYURAN , PETER DOYLE , SAURABH SHARMA , ANKUR SHAH , MURALI RAMADOSS
Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.
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