公开(公告)号：US20180041003A1

公开(公告)日：2018-02-08

申请号：US15231510

申请日：2016-08-08

Applicant: Intel Corporation

Inventor： Juan E. Dominguez ,  Myung Jin Yim

IPC: H01S5/022 ,  H01L23/00

CPC classification number: H01S5/02248 ,  H01L23/13 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/13147 ,  H01L2224/13611 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1426 ,  H01L2924/15151 ,  H01L2924/2064 ,  H01S5/02272 ,  H01L2924/01029 ,  H01L2924/01047

Abstract: Embodiments herein may relate to a chip-on-chip (CoC) package that includes a first integrated circuit (IC) die with an active side coupled with an active side of a second IC die. The CoC package may further include a substrate with a conductive metal post extending from a side of the substrate. An interposer may be positioned between, and coupled with the conductive metal post and the active side of the first IC die such that an area between an inactive side of the second IC die and the substrate is free of the interposer. Other embodiments may be described and/or claimed.

公开(公告)号：US12078853B2

公开(公告)日：2024-09-03

申请号：US17474484

申请日：2021-09-14

Applicant: Intel Corporation

Inventor： Vivek Raghunathan ,  Myung Jin Yim

IPC: G02B6/42 ,  G02B6/122 ,  G02B6/132 ,  H01L25/16

CPC classification number: G02B6/4206 ,  G02B6/122 ,  G02B6/132 ,  G02B6/42 ,  G02B6/4212 ,  G02B6/4225 ,  G02B6/428 ,  H01L25/167

Abstract: Semiconductor package with one or more optical die(s) embedded therein is disclosed. The optical die(s) may have one or more overlying interconnect layers. Electrical contact to the optical die may be via the one or more overlying interconnect layers. An optical waveguide may be disposed next to the optical die and embedded within the semiconductor package. An optical fiber may be optically coupled to the optical waveguide.

公开(公告)号：US11156788B2

公开(公告)日：2021-10-26

申请号：US16317796

申请日：2016-07-14

Applicant: Intel Corporation

Inventor： Vivek Raghunathan ,  Myung Jin Yim

IPC: G02B6/42 ,  H01L25/16 ,  G02B6/132 ,  G02B6/122

Abstract: Semiconductor package with one or more optical die(s) embedded therein is disclosed. The optical die(s) may have one or more overlying interconnect layers. Electrical contact to the optical die may be via the one or more overlying interconnect layers. An optical waveguide may be disposed next to the optical die and embedded within the semiconductor package. An optical fiber may be optically coupled to the optical waveguide.

公开(公告)号：US20180188448A1

公开(公告)日：2018-07-05

申请号：US15396467

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Myung Jin Yim

IPC: G02B6/122 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/50 ,  G02B6/4274 ,  H01L23/3675 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589

Abstract: In one embodiment, a microelectronic package structure comprises a substrate comprising at least one waveguide, a first instrument integrated circuit coupled to the substrate, a photonic engine coupled to the substrate and comprising an integrated circuit body, a transmit die. and a receive die. The photonic engine is positioned adjacent the at least one waveguide such that optical signals may be exchanged between the at least one waveguide and the transmit die and the at least one waveguide and the receive die. Other embodiments may be described.

公开(公告)号：US10014654B2

公开(公告)日：2018-07-03

申请号：US15100265

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Myung Jin Yim ,  Ansheng Liu ,  Valentin Yepanechnikov

IPC: H01L31/02 ,  H01L31/12 ,  H01L33/00 ,  H01S5/022 ,  H01S5/18 ,  H01L31/0232 ,  H01S5/024 ,  H01L21/56

CPC classification number: H01S5/02236 ,  H01L21/563 ,  H01L31/0232 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01S5/0226 ,  H01S5/02476 ,  H01S5/18 ,  H01L2924/00

Abstract: Optoelectronic packaging assemblies are provided that are useful for optical data, transfer In high performance computing applications, board to board in data centers, memory to CPU, switch/FPGA (field programmable gate array) for chip to chip interconnects, and memory extension. The packaging assemblies provide fine pitch flip chip interconnects and chip stacking assemblies with good thermo-mechanical reliability. Underfill dams and optical overhang regions and are provided for optical interconnection.

公开(公告)号：US09900102B2

公开(公告)日：2018-02-20

申请号：US14956191

申请日：2015-12-01

Applicant: Intel Corporation

Inventor： Olufemi I. Dosunmu ,  Myung Jin Yim ,  Ansheng Liu

IPC: H01L27/15 ,  H01L29/267 ,  H01L31/12 ,  H01L33/00 ,  H04B10/40 ,  H01L25/16 ,  H01L25/00

CPC classification number: H04B10/40 ,  H01L24/20 ,  H01L25/167 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73267

Abstract: Embodiments of the present disclosure provide an apparatus comprising an integrated circuit with a chip-on-chip and chip-on-substrate configuration. In one instance, the apparatus may include an optical transceiver with an opto-electronic component disposed in a first portion of a die, and a trace coupled with the opto-electronic component and disposed to extend to a surface in a second portion of the die adjacent to the first portion, to provide electrical connection for the integrated circuit and another integrated circuit to be coupled with the second portion of the die in a chip-on-chip configuration. The apparatus may include a second trace disposed in the second portion of the die to extend to the surface in the second portion, to provide electrical connection for the other integrated circuit and a substrate to be coupled with the second portion of the die in a chip-on-substrate configuration. Other embodiments may be described and/or claimed.

公开(公告)号：US20240264396A1

公开(公告)日：2024-08-08

申请号：US18624198

申请日：2024-04-02

Applicant: Intel Corporation

Inventor： Sang Yup Kim ,  Myung Jin Yim ,  Woosung Kim

IPC: G02B6/43 ,  G02B6/12 ,  G02B6/122 ,  G02B6/42

CPC classification number: G02B6/43 ,  G02B6/122 ,  G02B6/4212 ,  G02B6/4274 ,  G02B2006/12061

Abstract: An interposer apparatus for co-packaging an electronic integrated circuit and a photonic integrated circuit may include a dielectric substrate; an optical waveguide disposed on the dielectric substrate to optically couple the photonic integrated circuit disposed on one side of the dielectric substrate with at least one of another photonic integrated circuit disposed on the dielectric substrate or an optical device disposed on the dielectric substrate; and a metal interconnect disposed through the dielectric substrate to electrically couple the photonic integrated circuit disposed on the one side of the dielectric substrate with an electronic integrated circuit disposed on the other side of the dielectric substrate.

公开(公告)号：US20230091428A1

公开(公告)日：2023-03-23

申请号：US17992670

申请日：2022-11-22

Applicant: Intel Corporation

Inventor： Sang Yup Kim ,  Myung Jin Yim ,  Woosung Kim

IPC: G02B6/43 ,  G02B6/122 ,  G02B6/42

Abstract: An interposer apparatus for co-packaging an electronic integrated circuit and a photonic integrated circuit may include a dielectric substrate; an optical waveguide disposed on the dielectric substrate to optically couple the photonic integrated circuit disposed on one side of the dielectric substrate with at least one of another photonic integrated circuit disposed on the dielectric substrate or an optical device disposed on the dielectric substrate; and a metal interconnect disposed through the dielectric substrate to electrically couple the photonic integrated circuit disposed on the one side of the dielectric substrate with an electronic integrated circuit disposed on the other side of the dielectric substrate.

公开(公告)号：US20190172821A1

公开(公告)日：2019-06-06

申请号：US16267186

申请日：2019-02-04

Applicant: Intel Corporation

Inventor： Myung Jin Yim

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/367

Abstract: In one embodiment, a microelectronic package structure comprises a substrate comprising at least one waveguide, a first instrument integrated circuit coupled to the substrate, a photonic engine coupled to the substrate and comprising an integrated circuit body, a transmit die, and a receive die. The photonic engine is positioned adjacent the at least one waveguide such that optical signals may be exchanged between the at least one waveguide and the transmit die and the at least one waveguide and the receive die. Other embodiments may be described.

公开(公告)号：US20180348434A1

公开(公告)日：2018-12-06

申请号：US15609403

申请日：2017-05-31

Applicant: Intel Corporation

Inventor： Myung Jin Yim ,  Sang Yup Kim ,  Woosung Kim

IPC: G02B6/26 ,  H01L31/0232 ,  H01L25/16 ,  H01L23/00 ,  H01L23/367 ,  G02B6/34

Abstract: Embodiments herein may include apparatuses, systems, and processes related to a photonic die package with an edge lens that includes a photonic integrated circuit (IC) die, a lens coupled to the photonic IC die and disposed at an edge of the package to provide an optical path at the edge of the package for photon signals generated or received by the photonic IC die, and an electronic IC die coupled to the photonic IC die, where the electronic IC die is to process electrical signals received from the photonic IC die, and where the electronic IC die and the photonic IC die are in a stack formation to facilitate thermal energy conduction from the electronic IC die to the photonic IC die. Other embodiments may be described and/or claimed.