公开(公告)号：US10158034B2

公开(公告)日：2018-12-18

申请号：US15127207

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Kinyip Phoa ,  Nidhi Nidhi ,  Chia-Hong Jan ,  Walid M. Hafez ,  Yi Wei Chen

IPC: H01L31/044 ,  H01L31/0224 ,  H01L31/056 ,  H01L31/047 ,  H02S40/38 ,  H01L31/028 ,  H01L31/05 ,  H01L31/068 ,  H01L31/18

Abstract: An embodiment includes an apparatus comprising: a first photovoltaic cell; a first through silicon via (TSV) included in the first photovoltaic cell and passing through at least a portion of a doped silicon substrate, the first TSV comprising (a)(i) a first sidewall, which is doped oppositely to the doped silicon substrate, and (a)(ii) a first contact substantially filling the first TSV; and a second TSV included in the first photovoltaic cell and passing through at least another portion of the doped silicon substrate, the second TSV comprising (b)(i) a second sidewall, which comprises the doped silicon substrate, and (b)(ii) a second contact substantially filling the second TSV; wherein the first and second contacts each include a conductive material that is substantially transparent. Other embodiments are described herein.

公开(公告)号：US20170092726A1

公开(公告)日：2017-03-30

申请号：US15126812

申请日：2014-06-18

Applicant: INTEL CORPORATION

Inventor： Nidhi Nidhi ,  Chia-Hong Jan ,  Walid M. Hafez

IPC: H01L29/40 ,  H01L23/66 ,  H01L29/66 ,  H01L21/265 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/402 ,  H01L21/26513 ,  H01L23/66 ,  H01L29/1083 ,  H01L29/401 ,  H01L29/404 ,  H01L29/408 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

Abstract: Planar and non-planar field effect transistors with extended-drain structures, and techniques to fabricate such structures. In an embodiment, a field plate electrode is disposed over an extended-drain, with a field plate dielectric there between. The field plate is disposed farther from the transistor drain than the transistor gate. In a further embodiment, an extended-drain transistor has source and drain contact metal at approximately twice a pitch, of the field plate and the source and/or drain contact metal. In a further embodiment, an isolation dielectric distinct from the gate dielectric is disposed between the extended-drain and the field plate. In a further embodiment, the field plate may be directly coupled to one or more of the transistor gate electrode or a dummy gate electrode without requiring upper level interconnection. In an embodiment, a deep well implant may be disposed between a lightly-doped extended-drain and a substrate to reduce drain-body junction capacitance and improve transistor performance.

公开(公告)号：US12040395B2

公开(公告)日：2024-07-16

申请号：US16713648

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Ting Chang ,  Babak Fallahazad ,  Tanuj Trivedi ,  Jeong Dong Kim

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7816 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66704 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78696

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a substrate, a source region over the substrate, a drain region over the substrate, and a semiconductor body extending from the source region to the drain region. In an embodiment, the semiconductor body has a first region with a first conductivity type and a second region with a second conductivity type. In an embodiment, the semiconductor device further comprises a gate structure over the first region of the semiconductor body, where the gate structure is closer to the source region than the drain region.

公开(公告)号：US11862703B2

公开(公告)日：2024-01-02

申请号：US17870401

申请日：2022-07-21

Applicant: Intel Corporation

Inventor： Tanuj Trivedi ,  Rahul Ramaswamy ,  Jeong Dong Kim ,  Babak Fallahazad ,  Hsu-Yu Chang ,  Ting Chang ,  Nidhi Nidhi ,  Walid M. Hafez

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L29/42392 ,  H01L21/02532 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1062 ,  H01L29/165 ,  H01L29/66795

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

公开(公告)号：US11830818B2

公开(公告)日：2023-11-28

申请号：US17649637

申请日：2022-02-01

Applicant: Intel Corporation

Inventor： Kinyip Phoa ,  Jui-Yen Lin ,  Nidhi Nidhi ,  Chia-Hong Jan

IPC: H01L23/538 ,  H01L21/768

CPC classification number: H01L23/5384 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5386

Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.

公开(公告)号：US11688788B2

公开(公告)日：2023-06-27

申请号：US16209039

申请日：2018-12-04

Applicant: INTEL CORPORATION

Inventor： Johann C. Rode ,  Samuel J. Beach ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Han Wui Then ,  Walid Hafez

IPC: H01L21/02 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/513 ,  H01L21/022 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/28158 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: An integrated circuit includes a gate structure in contact with a portion of semiconductor material between a source region and a drain region. The gate structure includes gate dielectric and a gate electrode. The gate dielectric includes at least two hybrid stacks of dielectric material. Each hybrid stack includes a layer of low-κ dielectric and a layer of high-κ dielectric on the layer of low-κ dielectric, where the layer of high-κ dielectric has a thickness at least two times the thickness of the layer of low-κ dielectric. In some cases, the layer of low-κ dielectric has a thickness no greater than 1.5 nm. The layer of high-κ dielectric may be a composite layer that includes two or more layers of compositionally-distinct materials. The gate structure can be used with any number of transistor configurations but is particularly useful with respect to group III-V transistors.

公开(公告)号：US11658217B2

公开(公告)日：2023-05-23

申请号：US16242670

申请日：2019-01-08

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Glenn A. Glass ,  Sansaptak Dasgupta ,  Nidhi Nidhi ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L29/00 ,  H01L29/40 ,  H01L21/265 ,  H01L29/778 ,  H01L29/205

CPC classification number: H01L29/405 ,  H01L21/265 ,  H01L29/205 ,  H01L29/404 ,  H01L29/408 ,  H01L29/7786

Abstract: Disclosed herein are IC structures, packages, and devices assemblies that use ions or fixed charge to create field plate structures which are embedded in a dielectric material between gate and drain electrodes of a transistor. Ion- or fixed charge-based field plate structures may provide viable approaches to changing the distribution of electric field at a transistor drain to increase the breakdown voltage of a transistor without incurring the large parasitic capacitances associated with the use of metal field plates. In one aspect, an IC structure includes a transistor, a dielectric material between gate and drain electrodes of the transistor, and an ion- or fixed charge-based region within the dielectric material, between the gate and the drain electrodes. Such an ion- or fixed charge-based region realizes an ion- or fixed charge-based field plate structure. Optionally, the IC structure may include multiple ion- or fixed charge-based field plate structures.

公开(公告)号：US11626513B2

公开(公告)日：2023-04-11

申请号：US16218886

申请日：2018-12-13

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Nidhi Nidhi ,  Walid M. Hafez ,  Johann C. Rode ,  Paul Fischer ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Heli Chetanbhai Vora

IPC: H01L29/417 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/43 ,  H01L21/285 ,  H01L29/40 ,  H01L21/02 ,  H01L29/20

Abstract: Embodiments include a transistor and methods of forming a transistor. In an embodiment, the transistor comprises a semiconductor channel, a source electrode on a first side of the semiconductor channel, a drain electrode on a second side of the semiconductor channel, a polarization layer over the semiconductor channel, an insulator stack over the polarization layer, and a gate electrode over the semiconductor channel. In an embodiment, the gate electrode comprises a main body that passes through the insulator stack and the polarization layer, and a first field plate extending out laterally from the main body.

公开(公告)号：US20210074642A1

公开(公告)日：2021-03-11

申请号：US16074142

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Kinyip Phoa ,  Jui-Yen Lin ,  Nidhi Nidhi ,  Chia-Hong Jan

IPC: H01L23/538 ,  H01L21/768

Abstract: An apparatus includes a first metal layer, a second metal layer and a dielectric material. The first metal layer has a first thickness and a second thickness less than the first thickness, and the first metal layer comprises a first interconnect having a first thickness. The dielectric material extends between the first and second metal layers and directly contacts the first and second metal layers. The dielectric material includes a via that extends through the dielectric material. A metal material of the via directly contacts the first interconnect and the second metal layer.

公开(公告)号：US20200373421A1

公开(公告)日：2020-11-26

申请号：US16419179

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L29/778 ,  H01L29/20 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistor arrangements that may reduce nonlinearity of off-state capacitance of the III-N transistors. In various aspects, III-N transistor arrangements limit the extent of access regions of the transistors, compared to conventional implementations, which may limit the depletion of the access regions. Due to the limited extent of the depletion regions of a transistor, the off-state capacitance may exhibit less variability in values across different gate-source voltages and, hence, exhibit a more linear behavior during operation.