公开(公告)号：US20190044519A1

公开(公告)日：2019-02-07

申请号：US16020748

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Sean R. Atsatt ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H03K19/177

Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die, such that the programmable logic fabric may include a first region of programmable logic fabric and a second region of programmable logic fabric. The first region of programmable logic fabric is configured to be programmed with a circuit design that operates on a first set of data. The integrated circuit may also include network on chip (NOC) circuitry disposed on a second integrated circuit die, such that the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die.

公开(公告)号：US20180307783A1

公开(公告)日：2018-10-25

申请号：US15941983

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Thiam Khean Hah ,  Vamsi Nalluri ,  Herman Henry Schmit ,  Scott J. Weber ,  Randy Huang

IPC: G06F17/50 ,  G06N3/08 ,  G06N3/063 ,  G06N3/04

CPC classification number: G06F17/505 ,  G06N3/04 ,  G06N3/0635 ,  G06N3/08

Abstract: Systems and methods are included for efficiently implementing learned parameter systems (LPSs) on a programmable integrated circuit (PIC) via a computing engine. The computing engine receives an input set of learned parameters corresponding to use instances of an LPS. The computing engine reduces at least some redundancies and/or unnecessary operations using instance specific parameter values of the LPS, to generate a less redundant set of learned parameters and a corresponding less redundant LPS. The computing engine generates a netlist based on these, which may share computing resources of the PIC across multiple computations in accordance with the less redundant set of learned parameters and the corresponding less redundant LPS. The computing engine then programs the PIC with the netlist. That is, the netlist replaces use instances of at least some of the original learned parameters and its corresponding LPS and is executed instead of the original.

公开(公告)号：US20180218103A1

公开(公告)日：2018-08-02

申请号：US15422834

申请日：2017-02-02

Applicant: Intel Corporation

Inventor： Scott J. Weber ,  Carl Ebeling

IPC: G06F17/50

Abstract: A method for designing a system on a target device includes modifying a circuit to enable the circuit to support a plurality of threads at an instant of time. An interface is generated that enables one or more of the plurality of threads to be swapped out of an execution queue for accessing the circuit and that enables one or more other threads to be swapped into the execution queue for accessing the circuit, wherein at least one of the modifying and the generating is performed by a processor.

公开(公告)号：US12273282B2

公开(公告)日：2025-04-08

申请号：US18587744

申请日：2024-02-26

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H04L49/109 ,  H01L23/538 ,  H01L25/065 ,  H04L49/15

Abstract: This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.

公开(公告)号：US11611518B2

公开(公告)日：2023-03-21

申请号：US17528005

申请日：2021-11-16

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H01L25/065 ,  H04L12/933 ,  H04L49/109 ,  H04L49/15 ,  H01L23/538

Abstract: This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.

公开(公告)号：US20230056118A1

公开(公告)日：2023-02-23

申请号：US17893004

申请日：2022-08-22

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  James Ball ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H03K19/1776 ,  G11C7/10 ,  H01L25/065 ,  G11C5/02

Abstract: An integrated circuit device may include a programmable fabric die having programmable logic fabric and configuration memory that may configure the programmable logic fabric. The integrated circuit device may also include a base die that may provide fabric support circuitry, including memory and/or communication interfaces. The first die and the second die may be coupled using a multi-purpose interface that may allow communication between the first die and the second die. The multi-purpose interface may allow concurrent access to the base die by the programmable logic fabric and the configuration memory by using multiple channels over the multi-purpose interface.

公开(公告)号：US11520388B2

公开(公告)日：2022-12-06

申请号：US15855457

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Sean R. Atsatt ,  Scott J. Weber ,  Aravind Raghavendra Dasu ,  Ravi Prakash Gutala

IPC: G05B15/02 ,  G06F1/20 ,  H03K19/0175 ,  H03K19/003 ,  H03K19/00 ,  G06F1/3287 ,  H01L23/538 ,  G06F1/3296 ,  H01L25/18 ,  H01L23/367 ,  H01L23/00 ,  H01L23/34

Abstract: An integrated circuit assembly may include an integrated circuit having a plurality of programmable logic sectors and an interposer circuit positioned adjacent to the integrated circuit. The interposer circuit may include at least one voltage regulator that distributes a voltage to at least one of the plurality of programmable logic sectors and at least one thermal sensor that measures a temperature of the at least one of the plurality of programmable logic sectors.

公开(公告)号：US11296706B2

公开(公告)日：2022-04-05

申请号：US16020748

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Sean R. Atsatt ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H03K19/17772 ,  H03K19/1776 ,  H03K19/17768 ,  H03K19/17796 ,  H03K19/17758

Abstract: An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die, such that the programmable logic fabric may include a first region of programmable logic fabric and a second region of programmable logic fabric. The first region of programmable logic fabric is configured to be programmed with a circuit design that operates on a first set of data. The integrated circuit may also include network on chip (NOC) circuitry disposed on a second integrated circuit die, such that the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die.

公开(公告)号：US20220078136A1

公开(公告)日：2022-03-10

申请号：US17528005

申请日：2021-11-16

Applicant: Intel Corporation

Inventor： Kevin Clark ,  Scott J. Weber ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu

IPC: H04L12/933 ,  H01L25/065

Abstract: This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.

公开(公告)号：US11257526B2

公开(公告)日：2022-02-22

申请号：US15868304

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Scott J. Weber ,  Sean R. Atsatt ,  Ravi Prakash Gutala ,  Aravind Raghavendra Dasu ,  Jun Pin Tan

IPC: G11C5/02 ,  H03K19/1776 ,  G11C5/04 ,  G11C5/06

Abstract: An integrated circuit device may include programmable logic fabric on a first integrated circuit die and sector-aligned memory on a second integrated circuit die to enable large amounts of data to be rapidly processed by a sector of programmable logic of the programmable logic device. The programmable logic fabric may include a first and second sectors. The first sector may be programmed with a circuit design that operates on a first set of data. The sector-aligned memory may include a first sector of sector-aligned memory directly accessible by the first sector of programmable logic fabric and a second sector of sector-aligned memory directly accessible by the second sector of programmable logic fabric. The first sector of sector-aligned memory may store the first set of data.