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    INTEGRATED CLOCK GATE WITH CIRCUITRY TO FACILITATE CLOCK FREQUENCY DIVISION
    13.
    发明公开
    INTEGRATED CLOCK GATE WITH CIRCUITRY TO FACILITATE CLOCK FREQUENCY DIVISION 审中-公开

    公开(公告)号：US20240007087A1

    公开(公告)日：2024-01-04

    申请号：US17856887

    申请日：2022-07-01

    Applicant: Intel Corporation

    Inventor： Steven Hsu ,  Amit Agarwal ,  Simeon Realov ,  Mark Anders ,  Ram Krishnamurthy

    IPC: H03K3/037 ,  H03K19/21 ,  G06F1/06

    CPC classification number: H03K3/037 ,  H03K19/21 ,  G06F1/06

    Abstract: Techniques and mechanisms for an integrated clock gate (ICG) to selectively output a clock signal, and to provide frequency division functionality. In an embodiment, an ICG circuit comprises first circuitry which is coupled to receive a first clock signal, and second circuitry which is coupled to receive a control signal. The first circuitry provides a single edge triggered flip-flop functionality, and is coupled to communicate a feedback signal which the first circuitry is further coupled to receive. Based on the control signal and the feedback signal, the second circuitry performs an exclusive OR (XOR) operation to selectively enable the first circuitry to generate a second clock signal based on the first clock signal. In another embodiment, a frequency of the second clock signal is substantially equal to one half of a frequency of the first clock signal.

    LOW-POWER SINGLE-EDGE TRIGGERED FLIP-FLOP, AND TIME BORROWING INTERNALLY STITCHED FLIP-FLOP
    20.
    发明申请
    LOW-POWER SINGLE-EDGE TRIGGERED FLIP-FLOP, AND TIME BORROWING INTERNALLY STITCHED FLIP-FLOP 有权

    公开(公告)号：US20210281250A1

    公开(公告)日：2021-09-09

    申请号：US16813558

    申请日：2020-03-09

    Applicant: Intel Corporation

    Inventor： Steven Hsu ,  Amit Agarwal ,  Simeon Realov ,  Satish Damaraju ,  Ram Krishnamurthy

    IPC: H03K3/037 ,  G06F3/06 ,  G01R31/3177 ,  G06F1/06

    Abstract: A new family of shared clock single-edge triggered flip-flops that reduces a number of internal clock devices from 8 to 6 devices to reduce clock power. The static pass-gate master-slave flip-flop has no performance penalty compared to the flip-flops with 8 clock devices thus enabling significant power reduction. The flip-flop intelligently maintains the same polarity between the master and slave stages which enables the sharing of the master tristate and slave state feedback clock devices without risk of charge sharing across all combinations of clock and data toggling. Because of this, the state of the flip-flop remains undisturbed, and is robust across charge sharing noise. A multi-bit time borrowing internal stitched flip-flop is also described, which enables internal stitching of scan in a high performance time-borrowing flip-flop without incurring increase in layout area.

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