公开(公告)号：US11462541B2

公开(公告)日：2022-10-04

申请号：US16222934

申请日：2018-12-17

申请人： Intel Corporation

发明人： Juan G. Alzate Vinasco ,  Abhishek A. Sharma ,  Fatih Hamzaoglu ,  Bernhard Sell ,  Pei-Hua Wang ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Chieh-Jen Ku ,  Travis W. Lajoie ,  Umut Arslan

IPC分类号： H01L21/00 ,  H01L27/108 ,  H01L29/786 ,  H01L49/02 ,  H01L29/66 ,  H01L29/49 ,  H01L29/417

摘要： Embodiments herein describe techniques for a semiconductor device including a substrate oriented in a horizontal direction, and a memory cell including a transistor and a capacitor above the substrate. The transistor includes a gate electrode oriented in a vertical direction substantially orthogonal to the horizontal direction, and a channel layer oriented in the vertical direction, around the gate electrode and separated by a gate dielectric layer from the gate electrode. The capacitor is within an inter-level dielectric layer above the substrate. The capacitor includes a first plate coupled with a second portion of the channel layer of the transistor, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate of the capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.

公开(公告)号：US20220189957A1

公开(公告)日：2022-06-16

申请号：US17117978

申请日：2020-12-10

申请人： Intel Corporation

发明人： Sarah Atanasov ,  Abhishek A. Sharma ,  Bernhard Sell ,  Chieh-Jen Ku ,  Elliot Tan ,  Hui Jae Yoo ,  Noriyuki Sato ,  Travis W. Lajoie ,  Van H. Le

IPC分类号： H01L27/108 ,  G11C11/402 ,  H01L29/24

摘要： Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.

公开(公告)号：US20220173090A1

公开(公告)日：2022-06-02

申请号：US17210836

申请日：2021-03-24

申请人： Intel Corporation

发明人： Wilfred Gomes ,  Abhishek A. Sharma ,  Van H. Le ,  Doug B. Ingerly

IPC分类号： H01L25/18 ,  H01L25/065 ,  H01L23/00

摘要： Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages. One aspect relates to disaggregating 3D monolithic memory and compute functions to enable tight coupling for fast memory access at high bandwidth. Another aspect relates to microelectronic assemblies relate to nano-TSVs with 3D monolithic memory. Further aspects relate to die stitching and the use of glass carrier structures in microelectronic assemblies. Various aspects disclosed herein advantageously provide a robust set of implementations that may enable significant improvements in terms of optimizing performance of individual IC dies, microelectronic assemblies including one or more of such dies, and IC packages and devices including one or more of such microelectronic assemblies.

公开(公告)号：US20220158069A1

公开(公告)日：2022-05-19

申请号：US17592724

申请日：2022-02-04

申请人： Intel Corporation

发明人： Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Zachary R. Yoscovits ,  James S. Clarke ,  Van H. Le

IPC分类号： H01L39/22 ,  G06N10/00 ,  H01L39/02 ,  H01L39/24

摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.

公开(公告)号：US11322620B2

公开(公告)日：2022-05-03

申请号：US16648974

申请日：2017-12-29

申请人： Intel Corporation

发明人： Van H. Le ,  Ashish Agrawal ,  Seung Hoon Sung ,  Abhishek A. Sharma ,  Ravi Pillarisetty

IPC分类号： H01L29/786 ,  C30B29/08 ,  C30B29/40 ,  H01L27/088

摘要： Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.

公开(公告)号：US11296087B2

公开(公告)日：2022-04-05

申请号：US16473592

申请日：2017-03-31

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Shriram Shivaraman ,  Yih Wang ,  Tahir Ghani ,  Jack T. Kavalieros

IPC分类号： H01L29/417 ,  H01L29/49 ,  H01L27/108 ,  H01L29/45 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786

摘要： Embodiments herein describe techniques for a semiconductor device including a TFT having a gate electrode with a gate length determined by a spacer. Embodiments may include a gate electrode above a substrate, a channel layer above the gate electrode, and a source electrode, a drain electrode, and a spacer above the channel layer. The drain electrode may be separated from the source electrode by the spacer. The drain electrode and the source electrode may have different widths or include different materials. Furthermore, the spacer may overlap with the gate electrode, hence the gate length of the gate electrode may be determined by the spacer width. Other embodiments may be described and/or claimed.

公开(公告)号：US20220093517A1

公开(公告)日：2022-03-24

申请号：US17025166

申请日：2020-09-18

申请人： Intel Corporation

发明人： Aleksandar Aleksov ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Feras Eid ,  Randy B. Osborne ,  Van H. Le

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L23/49

摘要： Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include an interposer, including an organic dielectric material, and a microelectronic component coupled to the interposer by direct bonding.

公开(公告)号：US11251227B2

公开(公告)日：2022-02-15

申请号：US16480598

申请日：2017-03-31

申请人： Intel Corporation

发明人： Ravi Pillarisetty ,  Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC分类号： H01L27/22 ,  H01L27/24 ,  H01L27/108 ,  H01L29/66 ,  H01L29/78 ,  H01L43/12 ,  H01L45/00

摘要： A programmable array including a plurality of cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, the transistor including a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region and includes a width dimension equivalent to a width dimension of the body of the transistor. A method of forming an integrated circuit including forming bodies in a plurality rows on a substrate, each of the bodies including a programmable element and a first diffusion region, a second diffusion region and a channel of a transistor; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material; and replacing the masking material with an address line material.

公开(公告)号：US20210376102A1

公开(公告)日：2021-12-02

申请号：US17401692

申请日：2021-08-13

申请人： Intel Corporation

发明人： Ravi Pillarisetty ,  Van H. Le ,  Jeanette M. Roberts ,  David J. Michalak ,  James S. Clarke ,  Zachary R. Yoscovits

IPC分类号： H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/06

摘要： Disclosed herein are quantum dot devices with trenched substrates, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate having a trench disposed therein, wherein a bottom of the trench is provided by a first material, and a quantum well stack at least partially disposed in the trench. A material of the quantum well stack may be in contact with the bottom of the trench, and the material of the quantum well stack may be different from the first material.

公开(公告)号：US11183594B2

公开(公告)日：2021-11-23

申请号：US15938153

申请日：2018-03-28

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Shriram Shivaraman ,  Benjamin Chu-Kung ,  Yih Wang ,  Tahir Ghani

IPC分类号： H01L29/786 ,  H01L29/08 ,  H01L29/04 ,  H01L27/108 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L29/423 ,  H01L21/311

摘要： Disclosed herein are dual gate trench shaped thin film transistors and related methods and devices. Exemplary thin film transistor structures include a non-planar semiconductor material layer having a first portion extending laterally over a first gate dielectric layer, which is over a first gate electrode structure, and a second portion extending along a trench over the first gate dielectric layer, a second gate electrode structure at least partially within the trench, and a second gate dielectric layer between the second gate electrode structure and the first portion.