公开(公告)号：US11270998B2

公开(公告)日：2022-03-08

申请号：US15943537

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Yih Wang

IPC: G11C11/404 ,  H01L27/108 ,  G11C11/408 ,  G11C11/4091 ,  H01L27/06

Abstract: Described herein are apparatuses, methods, and systems associated with a memory circuit in a three-dimensional (3D) integrated circuit (IC). A control circuit of the memory circuit may include logic transistors in a logic layer of the 3D IC. The control circuit may further include one or more interconnects (e.g., local or global interconnects) and/or other devices in one or more front-side metal layers of the 3D IC. The memory circuit may further include a memory array in back-side metal layers of the 3D IC. The memory array may be formed in the back-side metal layers that are closest to the logic layer. Other embodiments may be described and claimed.

公开(公告)号：US11121073B2

公开(公告)日：2021-09-14

申请号：US15943565

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Travis Lajoie ,  Abhishek Sharma ,  Juan Alzate-Vinasco ,  Chieh-Jen Ku ,  Shem Ogadhoh ,  Allen Gardiner ,  Blake Lin ,  Yih Wang ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/108 ,  H01L23/532

Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.

公开(公告)号：US11088146B2

公开(公告)日：2021-08-10

申请号：US16474885

申请日：2017-04-04

Applicant: INTEL CORPORATION

Inventor： Yih Wang

IPC: H01L27/108

Abstract: An embedded dynamic random-access memory cell includes a wordline to supply a gate signal, a selector thin-film transistor (TFT) above the wordline and that includes an active layer and is configured to control transfer of a memory state of the memory cell between a first region and a second region of the active layer in response to the gate signal, a bitline to transfer the memory state and coupled to and above the first region of the active layer, a storage node coupled to and above the second region of the active layer, and a metal-insulator-metal capacitor coupled to and above the storage node and configured to store the memory state. In an embodiment, the wordline is formed in a back end of line process for interconnecting logic devices formed in a front end of line process below the wordline, and the selector TFT is formed in a thin-film process.

公开(公告)号：US10438640B2

公开(公告)日：2019-10-08

申请号：US16052552

申请日：2018-08-01

Applicant: Intel Corporation

Inventor： Liqiong Wei ,  Fatih Hamzaoglu ,  Yih Wang ,  Nathaniel J. August ,  Blake C. Lin ,  Cyrille Dray

IPC: G11C11/16 ,  G11C29/02 ,  G11C13/00

Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

公开(公告)号：US20180286916A1

公开(公告)日：2018-10-04

申请号：US15575667

申请日：2015-06-02

Applicant: Intel Corporation

Inventor： Yih Wang ,  Patrick Morrow

IPC: H01L27/22 ,  H01L43/08 ,  H01L45/00 ,  H01L27/24 ,  H01L43/02

CPC classification number: H01L27/226 ,  G11C11/161 ,  G11C13/0002 ,  G11C2213/71 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2454 ,  H01L43/02 ,  H01L43/08 ,  H01L45/04 ,  H01L45/1233

Abstract: A microelectronic memory having metallization layers formed on a back side of a substrate, wherein the metallization layers on back side may be used for the formation of source lines and word lines. Such a configuration may allow for a reduction in bit cell area, a higher memory array density, and lower source line and word line resistances. Furthermore, such a configuration may also provide the flexibility to independently optimize interconnect performance for logic and memory circuits.

公开(公告)号：US10068628B2

公开(公告)日：2018-09-04

申请号：US14129277

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Liqiong Wei ,  Fatih Hamzaoglu ,  Yih Wang ,  Nathaniel J. August ,  Blake C. Lin ,  Cyrille Dray

IPC: G11C11/16 ,  G11C29/02 ,  G11C13/00

Abstract: Apparatuses for improving resistive memory energy efficiency are provided. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

公开(公告)号：US20170358740A1

公开(公告)日：2017-12-14

申请号：US15596650

申请日：2017-05-16

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Tahir Ghani ,  Joseph M. Steigerwald ,  John H. Epple ,  Yih Wang

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/08

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

公开(公告)号：US09666268B2

公开(公告)日：2017-05-30

申请号：US14703723

申请日：2015-05-04

Applicant: Intel Corporation

Inventor： Yih Wang ,  Muhammad M. Khellah ,  Fatih Hamzaoglu

IPC: G11C7/00 ,  G11C11/419 ,  G11C5/14 ,  G11C11/4074

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C5/148 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417

Abstract: Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.

公开(公告)号：US09041146B2

公开(公告)日：2015-05-26

申请号：US13994716

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Kevin J. Lee ,  Tahir Ghani ,  Joseph M. Steigerwald ,  John H. Epple ,  Yih Wang

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L27/222 ,  H01L27/226 ,  H01L43/08

Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) with an upper MTJ layer, lower MTJ layer, and tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein.

Abstract translation: 实施例将逻辑芯片内的诸如自旋转矩传递磁阻随机存取存储器（STT-MRAM）的存储器集成。 STT-MRAM包括具有上部MTJ层，较低MTJ层和直接接触上层MTJ层和下层MTJ层的隧道势垒的磁隧道结（MTJ）; 其中上MTJ层包括上MTJ层侧壁，下MTJ层包括水平地偏离上MTJ层的下MTJ侧壁。 另一个实施例包括包含MTJ的存储区域和位于衬底上的逻辑区域; 其中水平面与MTJ相邻，邻近MTJ的第一层间电介质（ILD）材料和包含在逻辑区域中的第二ILD材料，第一和第二ILD材料彼此不相等。 在一个实施例中，第一和第二ILD直接彼此接触。 本文描述了其它实施例。

公开(公告)号：US09013941B2

公开(公告)日：2015-04-21

申请号：US13839174

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Swaroop Ghosh ,  Mesut Meterelliyoz ,  Faith Hamzaoglu ,  Yih Wang ,  Kevin X. Zhang

IPC: G11C7/00 ,  G11C11/4091 ,  G11C11/56 ,  G11C7/06 ,  G11C7/08

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/08 ,  G11C11/5642

Abstract: Disclosed is a pulsed sense amplifier approach for resolving data on a bit line. A chip is provided which comprises a sense amplifier coupled to first and second DRAM bitlines; and a circuit having a trigger node coupled to the sense amp to transition it from a first state to a second state to trigger the sense amp, the circuit having an element to impede the transition once it is initiated. A chip is described which comprises: a DRAM array having a plurality of bitlines; sense amplifiers to resolve data on the bit lines, and a circuit to slow down resolution of the data by the sense amps after they have been triggered to resolve the data.

Abstract translation: 公开了用于解析位线上的数据的脉冲读出放大器方法。 提供了一种芯片，其包括耦合到第一和第二DRAM位线的读出放大器; 以及电路，其具有耦合到所述感测放大器的触发节点，以将其从第一状态转换到第二状态以触发所述感测放大器，所述电路具有阻止所述转换的元件。 描述了一种芯片，其包括：具有多个位线的DRAM阵列; 用于解析位线上的数据的读出放大器，以及在触发解调数据之后通过感测放大器降低数据分辨率的电路。