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11.
公开(公告)号:US20150380560A1
公开(公告)日:2015-12-31
申请号:US14725361
申请日:2015-05-29
Applicant: Japan Display Inc.
Inventor: Miyuki ISHIKAWA , Arichika ISHIDA , Masayoshi FUCHI , Hajime WATAKABE , Takashi OKADA
IPC: H01L29/786 , H01L29/417 , H01L21/441 , H01L29/66
CPC classification number: H01L29/7869 , H01L21/441 , H01L21/465 , H01L21/467 , H01L27/1225 , H01L27/124 , H01L27/3272 , H01L29/41733 , H01L29/66969 , H01L29/78603 , H01L29/78633 , H01L29/78696
Abstract: According to one embodiment, a semiconductor device includes contact holes passing through a source region of a drain region of an interlayer insulating film and oxide semiconductor layer to reach an insulating substrate, wherein a source electrode and a drain electrode are formed inside the contact holes, respectively.
Abstract translation: 根据一个实施例,半导体器件包括穿过层间绝缘膜和氧化物半导体层的漏极区域的源极区域的接触孔,以到达绝缘基板,其中源极电极和漏电极形成在接触孔内部, 分别。
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公开(公告)号:US20240130213A1
公开(公告)日:2024-04-18
申请号:US18485334
申请日:2023-10-12
Applicant: Japan Display Inc.
Inventor: Arichika ISHIDA
CPC classification number: H10K71/861 , H10K59/1201 , H10K59/8722
Abstract: According to one embodiment, a method of manufacturing a display device, includes forming a plurality of display elements each including a lower electrode, an organic layer which covers the lower electrode and an upper electrode which covers the organic layer, forming a first sealing layer which seals the plurality of display elements, individually, inspecting the plurality of display elements to determine whether any of the plurality of display elements entails a defect and forming, when in the inspection, it is confirmed that there is a defective one of the display elements, a repair hole which penetrates the first sealing layer which seals the defective one of the display elements.
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公开(公告)号:US20230345796A1
公开(公告)日:2023-10-26
申请号:US18297663
申请日:2023-04-10
Applicant: Japan Display Inc.
Inventor: Arichika ISHIDA
CPC classification number: H10K59/871 , H10K71/00 , H10K2102/351
Abstract: According to one embodiment, a display device includes a lower electrode, a rib including a pixel aperture, a partition on the rib, an upper electrode contacting the partition, an organic layer between the lower and upper electrodes, and a sealing layer covering a display element and the partition, the display element including the lower electrode, the upper electrode and the organic layer. The sealing layer includes a first portion which is located above the rib and has a first thickness, and a second portion which is located above the lower electrode exposed from the rib through the pixel aperture and has a second thickness less than the first thickness.
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公开(公告)号:US20180081211A1
公开(公告)日:2018-03-22
申请号:US15826946
申请日:2017-11-30
Applicant: Japan Display Inc.
Inventor: Arichika ISHIDA , Yasushi KAWATA
IPC: G02F1/1333 , H01L25/16 , H01L51/00
CPC classification number: G02F1/1333 , G02F1/133305 , G02F1/133351 , G02F2001/133302 , G02F2001/133354 , G02F2201/54 , H01L51/0097 , H01L2924/0002 , Y02P70/521 , H01L2924/00
Abstract: According to one embodiment, a display device includes a first substrate including a first resin substrate having a first thermal expansion coefficient, and a first barrier layer having a second thermal expansion coefficient which is lower than the first thermal expansion coefficient, a second substrate including a second resin substrate having a third thermal expansion coefficient which is equal to the first thermal expansion coefficient, and a second barrier layer having a fourth thermal expansion coefficient which is lower than the third thermal expansion coefficient and is equal to the first thermal expansion coefficient, and a display element located between the first resin substrate and the second resin substrate.
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公开(公告)号:US20180013006A1
公开(公告)日:2018-01-11
申请号:US15713077
申请日:2017-09-22
Applicant: Japan Display Inc.
Inventor: Miyuki ISHIKAWA , Arichika ISHIDA , Masayoshi FUCHI , Hajime WATAKABE , Takashi OKADA
IPC: H01L29/786 , H01L29/417 , H01L27/32 , H01L27/12 , H01L21/467 , H01L21/465 , H01L29/66 , H01L21/441
CPC classification number: H01L29/7869 , H01L21/441 , H01L21/465 , H01L21/467 , H01L27/1225 , H01L27/124 , H01L27/3272 , H01L29/41733 , H01L29/66969 , H01L29/78603 , H01L29/78633 , H01L29/78696
Abstract: According to one embodiment, a semiconductor device includes contact holes passing through a source region of a drain region of an interlayer insulating film and oxide semiconductor layer to reach an insulating substrate, wherein a source electrode and a drain electrode are formed inside the contact holes, respectively.
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公开(公告)号:US20160211177A1
公开(公告)日:2016-07-21
申请号:US14996323
申请日:2016-01-15
Applicant: Japan Display Inc.
Inventor: lsao SUZUMURA , Arichika ISHIDA , Hidekazu MIYAKE , Hiroto MIYAKE , Yohei YAMAGUCHI
IPC: H01L21/768 , H01L29/66 , H01L29/417 , H01L21/02
CPC classification number: H01L21/76895 , H01L21/022 , H01L21/32136 , H01L21/465 , H01L21/78 , H01L29/41733 , H01L29/45 , H01L29/4908 , H01L29/66969 , H01L29/7869
Abstract: According to one embodiment, a method of manufacturing a thin-film transistor includes forming a semiconductor layer on a gate electrode with an insulating layer 12 being interposed, forming interconnect formation layers on the semiconductor layer, forming a plurality of interconnects and electrodes by patterning the interconnect formation layers through etching, patterning the semiconductor layer in an island shape through etching after forming the electrodes, exposing a channel region of the semiconductor layer by etching a part of the electrodes on the semiconductor layer, and forming a protective layer so as to overlap the interconnects, the electrodes and the semiconductor layer having the island shape.
Abstract translation: 根据一个实施例,制造薄膜晶体管的方法包括在绝缘层12插入的栅电极上形成半导体层,在半导体层上形成互连形成层,通过图案化形成多个互连和电极 通过蚀刻进行互连形成层,在形成电极之后通过蚀刻将半导体层图案化为岛状,通过蚀刻半导体层上的一部分电极来暴露半导体层的沟道区域,并形成保护层以重叠 互连,电极和具有岛状的半导体层。
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公开(公告)号:US20160172503A1
公开(公告)日:2016-06-16
申请号:US15051786
申请日:2016-02-24
Applicant: Japan Display Inc.
Inventor: Masato HIRAMATSU , Masayoshi FUCHI , Arichika ISHIDA
IPC: H01L29/786 , H01L21/443 , H01L29/66 , H01L29/24
CPC classification number: H01L29/7869 , H01L21/02164 , H01L21/02211 , H01L21/02214 , H01L21/02271 , H01L21/02565 , H01L21/0262 , H01L21/443 , H01L21/465 , H01L29/24 , H01L29/4908 , H01L29/66969 , H01L29/78696
Abstract: According to one embodiment, a thin-film transistor comprises an oxide semiconductor layer formed on a part of a substrate, a first gate insulator film of a silicon dioxide film formed on the oxide semiconductor layer and by the CVD method with a silane-based source gas, a second gate insulator film of a silicon dioxide film formed on the first gate insulator film by the CVD method with a TEOS source gas, and a gate electrode formed on the second gate insulator film.
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公开(公告)号:US20240184177A1
公开(公告)日:2024-06-06
申请号:US18428228
申请日:2024-01-31
Applicant: Japan Display Inc.
Inventor: Yohei YAMAGUCHI , Arichika ISHIDA , Hidekazu MIYAKE , Hiroto MIYAKE , Isao SUZUMURA
IPC: G02F1/1368 , G02F1/1343 , G02F1/1362 , H01L27/12 , H01L29/423 , H01L29/786
CPC classification number: G02F1/1368 , G02F1/134309 , G02F1/13439 , G02F1/136209 , G02F1/136227 , H01L27/1225 , H01L29/78633 , H01L29/7869 , G02F1/136218 , G02F1/13685 , G02F2202/10 , H01L29/42384
Abstract: According to one embodiment, a semiconductor device includes an insulating substrate, a first metal layer on the insulating substrate, a first insulating layer on the insulating substrate and the first metal layer, a semiconductor layer on the first insulating layer, a second insulating layer on the semiconductor layer and the first insulating layer, a second metal layer on the second insulating layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer. The first metal layer overlaps the second metal layer. A third metal layer contacts a top surface of the second metal layer and a top surface of the first metal layer.
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公开(公告)号:US20230345769A1
公开(公告)日:2023-10-26
申请号:US18299078
申请日:2023-04-12
Applicant: Japan Display Inc.
Inventor: Arichika ISHIDA
IPC: H10K59/122 , H10K59/80 , H10K59/12
CPC classification number: H10K59/122 , H10K59/80515 , H10K59/1201
Abstract: According to one embodiment, a display device includes a lower electrode, a rib covering a part of the lower electrode and includes a pixel aperture overlapping the lower electrode, an upper electrode facing the lower electrode, and an organic layer between the lower and upper electrodes. The lower electrode includes a metal layer including a first peripheral portion covered with the rib, and a first central portion exposed from the rib through the pixel aperture, and a conductive oxide layer including a second peripheral portion located on the rib, and a second central portion which is in contact with the first central portion through the pixel aperture.
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公开(公告)号:US20170343845A1
公开(公告)日:2017-11-30
申请号:US15662385
申请日:2017-07-28
Applicant: Japan Display Inc.
Inventor: Yohei YAMAGUCHI , Arichika ISHIDA , Hidekazu MIYAKE , Hiroto MIYAKE , Isao SUZUMURA
IPC: G02F1/1368 , G02F1/1343 , G02F1/1362 , H01L29/786 , H01L27/12 , H01L29/423
CPC classification number: G02F1/1368 , G02F1/134309 , G02F1/13439 , G02F1/136209 , G02F1/136227 , G02F2001/136218 , G02F2001/13685 , G02F2202/10 , H01L27/1225 , H01L29/42384 , H01L29/78633 , H01L29/7869
Abstract: According to one embodiment, a display device includes an insulating substrate, a thin-film transistor including a semiconductor layer formed on a layer above the insulating substrate, a gate electrode which at least partly overlaps the semiconductor layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer, and a light shielding layer formed between the thin-film transistor and the insulating substrate to at least partly overlap the semiconductor layer, the light shielding layer electrically connected to the gate electrode.
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