公开(公告)号：US20210320158A1

公开(公告)日：2021-10-14

申请号：US17304569

申请日：2021-06-23

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Toshihide JINNAI ,  Isao SUZUMURA ,  Hajime WATAKABE ,  Ryo ONODERA

IPC: H01L27/32 ,  G02F1/1333

Abstract: The purpose of the present invention is to increase ON current of the oxide semiconductor thin film transistor. An example of the structure that attains the purpose is: a display device having a substrate and a thin film transistor of an oxide semiconductor formed on the substrate including: a thickness of a source region and a drain region is thicker than a thickness of a channel region of the oxide semiconductor, the channel region has projections at portions contacting the source region and the drain region, a thickness of the projection is thicker than a thickness of the center of the channel region, and a thickness of the projection is thicker than a thickness of the source region and the drain region.

公开(公告)号：US20210240042A1

公开(公告)日：2021-08-05

申请号：US17159154

申请日：2021-01-27

Applicant: Japan Display Inc.

Inventor： Ryo ONODERA ,  Hajime WATAKABE ,  Akihiro HANADA

IPC: G02F1/1362

Abstract: A high definition display device is provided. The display device includes an array substrate, and an opposing substrate. The array substrate has a substrate, and on the substrate, a first pixel having a first color filter and a second pixel having a second color filter disposed adjacent to the first pixel. Each of the first color filter and the second color filter has a first dielectric layer, a transmissive layer disposed on the first dielectric layer, and a second dielectric layer disposed on the transmissive layer. The transmissive layer of the first color filter has a first film thickness, and the transmissive layer of the second color filter has a second film thickness larger than the first film thickness. On the transmissive layer of the second color filter, a first layer different from the transmissive layer is disposed on a side of the transmissive layer of the first color filter. A height of a bottom face of the first layer is equal to the first film thickness.

公开(公告)号：US20200259020A1

公开(公告)日：2020-08-13

申请号：US16785662

申请日：2020-02-10

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Tomoyuki ITO ,  Toshihide JINNAI ,  lsao SUZUMURA ,  Akihiro HANADA ,  Ryo ONODERA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L21/426 ,  H01L21/4757 ,  H01L21/4763 ,  H01L29/66

Abstract: A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.

公开(公告)号：US20180013006A1

公开(公告)日：2018-01-11

申请号：US15713077

申请日：2017-09-22

Applicant: Japan Display Inc.

Inventor： Miyuki ISHIKAWA ,  Arichika ISHIDA ,  Masayoshi FUCHI ,  Hajime WATAKABE ,  Takashi OKADA

IPC: H01L29/786 ,  H01L29/417 ,  H01L27/32 ,  H01L27/12 ,  H01L21/467 ,  H01L21/465 ,  H01L29/66 ,  H01L21/441

CPC classification number: H01L29/7869 ,  H01L21/441 ,  H01L21/465 ,  H01L21/467 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3272 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78633 ,  H01L29/78696

Abstract: According to one embodiment, a semiconductor device includes contact holes passing through a source region of a drain region of an interlayer insulating film and oxide semiconductor layer to reach an insulating substrate, wherein a source electrode and a drain electrode are formed inside the contact holes, respectively.

公开(公告)号：US20250113617A1

公开(公告)日：2025-04-03

申请号：US18887079

申请日：2024-09-17

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Akihiro HANADA ,  Masahiro WATABE

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/786

Abstract: A semiconductor device includes a first gate electrode, an oxide semiconductor layer including a first oxide semiconductor having a polycrystalline structure over the first gate electrode, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, and a second gate electrode overlapping the first gate electrode and the oxide semiconductor layer over the source electrode and the drain electrode. In a plan view, the second gate electrode is located with a space from each of the source electrode and the drain electrode. The second gate electrode is electrically connected to the first gate electrode.

公开(公告)号：US20250089302A1

公开(公告)日：2025-03-13

申请号：US18960197

申请日：2024-11-26

Applicant: Japan Display Inc.

Inventor： Takaya TAMARU ,  Masashi TSUBUKU ,  Hajime WATAKABE ,  Toshinari SASAKI

IPC: H01L29/786 ,  H01L29/66

Abstract: A semiconductor device includes a metal oxide layer containing aluminum as a main component above an insulating surface, an oxide semiconductor layer on the metal oxide layer; a gate electrode facing the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode, wherein a water contact angle on an upper surface of the metal oxide layer is 20° or lower.

公开(公告)号：US20240402552A1

公开(公告)日：2024-12-05

申请号：US18798914

申请日：2024-08-09

Applicant: Japan Display Inc.

Inventor： Toshihide JINNAI ,  Hajime WATAKABE ,  Akihiro HANADA ,  Ryo ONODERA ,  lsao SUZUMURA

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/786 ,  H10K59/131

Abstract: A display device including a substrate having a first TFT of an oxide semiconductor and a second TFT of a polysilicon semiconductor comprising: the oxide semiconductor is covered by a first insulating film, a first drain electrode is connected to the oxide semiconductor via a first through hole formed in the first insulating film, a first source electrode is connected to the oxide semiconductor via second through hole formed in the first insulating film in the first TFT, a second insulating film is formed covering the first drain electrode and the first source electrode, a drain wiring connects to the first drain electrode via a third through hole formed in the second insulating film, a source wiring is connected to the first source electrode via a fourth through hole formed in the second insulating film.

公开(公告)号：US20240379865A1

公开(公告)日：2024-11-14

申请号：US18651909

申请日：2024-05-01

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA ,  Masahiro WATABE

IPC: H01L29/786 ,  H01L29/417

Abstract: A semiconductor device according to an embodiment of the present invention includes: a gate electrode; a gate insulating layer; a metal oxide layer containing aluminum as a main component above the gate insulating layer; an oxide semiconductor layer having a polycrystalline structure above the metal oxide layer; a source electrode and a drain electrode contacting the oxide semiconductor layer from above the oxide semiconductor layer; and an insulating layer above the source electrode and the drain electrode, wherein a linear mobility of the semiconductor device is larger than 20 cm2/Vs when (Vg−Vth)×Cox=5×10−7 C/cm2, in the case where the Vg is a voltage supplied to the gate electrode, the Vth is a threshold voltage of the semiconductor device, and the Cox is an electrostatic capacitance of the gate insulating layer sandwiched by the gate electrode and the oxide semiconductor layer.

公开(公告)号：US20240332427A1

公开(公告)日：2024-10-03

申请号：US18604840

申请日：2024-03-14

Applicant: Japan Display Inc.

Inventor： Marina MOCHIZUKI ,  Masahiro WATABE ,  Masashi TSUBUKU ,  Hajime WATAKABE ,  Toshinari SASAKI ,  Takaya TAMARU ,  Ryo ONODERA

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/6675

Abstract: A semiconductor device includes a gate electrode, a gate insulating layer over the gate electrode, a metal oxide layer over the gate insulating layer, an oxide semiconductor layer having a polycrystalline structure over the metal oxide layer, a source electrode and a drain electrode over the oxide semiconductor layer, and an interlayer insulating layer in contact with the oxide semiconductor layer, the interlayer insulating layer covering the source electrode and the drain electrode, wherein the oxide semiconductor layer includes a first region overlapping one of the source electrode and the drain electrode and a second region in contact with the interlayer insulating layer, and a difference between a thickness of the first region and a thickness of the second region is 5 nm or less.

公开(公告)号：US20240312999A1

公开(公告)日：2024-09-19

申请号：US18588249

申请日：2024-02-27

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Marina MOCHIZUKI ,  Ryo ONODERA

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/1251

Abstract: A semiconductor device includes a first transistor on a substrate and a second transistor on the first transistor. The first transistor includes a first gate electrode on the substrate, a first insulating film on the first gate electrode, a first oxide semiconductor layer on the first insulating film, having a region overlapping the first gate electrode, and having a polycrystalline structure, a second insulating film on the first oxide semiconductor layer, and a second gate electrode on the second insulating film. The second transistor includes a third gate electrode on the second insulating film, a third insulating film on the third gate electrode, a second oxide semiconductor layer on the third insulating film and having a region overlapping the third gate electrode, a fourth insulating film on the second oxide semiconductor layer, and a fourth gate electrode on the fourth insulating film.