公开(公告)号：US08027200B2

公开(公告)日：2011-09-27

申请号：US12195552

申请日：2008-08-21

申请人： Vishal Sarin ,  William Saiki ,  Frankie F. Roohparvar

发明人： Vishal Sarin ,  William Saiki ,  Frankie F. Roohparvar

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621

摘要： Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to increase the threshold voltage of the memory cells being programmed. A negative voltage pulse is applied to the word line after the programming pulse to force any electrons trapped in the tunnel oxide of memory cells being programmed back into the tunnel region. After the negative pulse, a program verify operation is performed.

摘要翻译： 公开了减少快速充电损失效应的方法，编程方法，存储器件和存储器系统。 在一种这样的方法中，将编程脉冲施加到字线以增加正被编程的存储器单元的阈值电压。 在编程脉冲之后，将负电压脉冲施加到字线，以将捕获在存储器单元的隧道氧化物中的任何电子强制编程回隧道区域。 在负脉冲之后，执行程序验证操作。

公开(公告)号：US20060123280A1

公开(公告)日：2006-06-08

申请号：US10991702

申请日：2004-11-17

申请人： Hieu Tran ,  Anh Ly ,  Sang Nguyen ,  Vishal Sarin ,  Hung Nguyen ,  William Saiki ,  Loc Hoang

发明人： Hieu Tran ,  Anh Ly ,  Sang Nguyen ,  Vishal Sarin ,  Hung Nguyen ,  William Saiki ,  Loc Hoang

IPC分类号： G11C29/00

CPC分类号： G11C11/5621 ,  G11C16/04 ,  G11C29/50 ,  G11C29/50004

摘要： A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.

公开(公告)号：US08213233B2

公开(公告)日：2012-07-03

申请号：US13236765

申请日：2011-09-20

申请人： Vishal Sarin ,  William Saiki ,  Frankie F. Roohparvar

发明人： Vishal Sarin ,  William Saiki ,  Frankie F. Roohparvar

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621

摘要： Methods for reducing quick charge loss effects, methods for programming, memory devices, memory devices, and memory systems are disclosed. In one such method, a programming pulse is applied to the word line to increase the threshold voltage of the memory cells being programmed. A negative voltage pulse is applied to the word line after the programming pulse to force any electrons trapped in the tunnel oxide of memory cells being programmed back into the tunnel region. After the negative pulse, a program verify operation is performed.

摘要翻译： 公开了减少快速充电损失效应的方法，编程方法，存储器件和存储器系统。 在一种这样的方法中，将编程脉冲施加到字线以增加正被编程的存储器单元的阈值电压。 在编程脉冲之后，将负电压脉冲施加到字线，以将捕获在存储器单元的隧道氧化物中的任何电子强制编程回隧道区域。 在负脉冲之后，执行程序验证操作。

公开(公告)号：US20110032761A1

公开(公告)日：2011-02-10

申请号：US12909414

申请日：2010-10-21

申请人： Vishal Sarin ,  Dzung Nguyen ,  Jonathan Pabustan ,  Jung Sheng Hoei ,  Jason Guo ,  William Saiki

发明人： Vishal Sarin ,  Dzung Nguyen ,  Jonathan Pabustan ,  Jung Sheng Hoei ,  Jason Guo ,  William Saiki

IPC分类号： G11C16/16 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/344 ,  G11C16/0483 ,  G11C16/3445

摘要： Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.

摘要翻译： 公开了诸如涉及包括存储器块的闪速存储器件的方法和装置。 存储块包括基本上彼此平行延伸的多条数据线，以及多个存储单元。 一种这样的方法包括擦除存储器单元; 并对存储器单元执行擦除验证。 擦除验证包括由一个存储器单元确定耦合到数据线之一中的各个存储器单元是否已经被擦除的一个存储器单元。 该方法还可以包括执行至少部分地基于擦除验证的结果来选择性地重新擦除未故障存储器单元的重擦除操作。

公开(公告)号：US20050093615A1

公开(公告)日：2005-05-05

申请号：US10990786

申请日：2004-11-16

申请人： William Saiki ,  Hieu Tran ,  Sakhawat Khan

发明人： William Saiki ,  Hieu Tran ,  Sakhawat Khan

IPC分类号： G11C16/30 ,  H02M3/07 ,  H03B1/00

CPC分类号： H02M3/07 ,  G11C16/30

摘要： A high voltage generator provides high voltage signals with different regulated voltage levels. A charge pump generates the high voltage, and includes a quadrature phase forward and backward Vt-canceling high-voltage self-biasing charge pump with a powerup-assist diode. A high voltage series regulator generates the high voltage supply levels, and includes slew rate enhancement and trimmable diode regulation. A nested loop regulator eliminates shunt regulation.

公开(公告)号：US20050024956A1

公开(公告)日：2005-02-03

申请号：US10628979

申请日：2003-07-28

申请人： Hieu Tran ,  Sakhawat Khan ,  William Saiki ,  George Korsh

发明人： Hieu Tran ,  Sakhawat Khan ,  William Saiki ,  George Korsh

IPC分类号： G11C7/00 ,  G11C11/56 ,  G11C29/00 ,  G11C29/50

CPC分类号： G11C29/50 ,  G11C11/5621 ,  G11C16/04 ,  G11C29/027 ,  G11C29/50004 ,  G11C29/82 ,  G11C2029/0409

摘要： A digital multilevel bit memory array system comprises regular memory arrays and redundant memory arrays. A regular y-driver corresponds to each memory array to read or write contents to a multilevel bit memory cell and compare the read cell content to reference voltage levels to determine the data stored in the corresponding memory cell. Likewise, similar functions are performed by the redundant y-driver circuit for the redundant memory array. During the verification of the contents of the memory cell, if the read voltage is outside a certain margin requirement for a level of the reference voltage, a signal is generated in real time so that data from the bad y-driver is not output and data from the redundant y-driver corresponding to the redundant memory array is read out. The memory array system may also include a fractional multilevel redundancy.

摘要翻译： 数字多电平位存储器阵列系统包括常规存储器阵列和冗余存储器阵列。 常规y驱动器对应于每个存储器阵列以将内容读取或写入多级位存储器单元，并将读取的单元内容与参考电压电平进行比较，以确定存储在相应存储器单元中的数据。 类似的功能由冗余的y驱动电路执行，用于冗余存储器阵列。 在验证存储单元的内容期间，如果读取电压超出参考电压电平的一定余量要求，则实时生成信号，以便不输出来自不良y驱动器的数据和数据 从对应于冗余存储器阵列的冗余y驱动器读出。 存储器阵列系统还可以包括分数多级冗余。

公开(公告)号：US5848026A

公开(公告)日：1998-12-08

申请号：US986506

申请日：1997-12-08

申请人： Srinivas Ramamurthy ,  Jinglun Eugene Tam ,  Geoffrey S. Gongwer ,  James Fahey, Jr. ,  Neal Berger ,  William Saiki

发明人： Srinivas Ramamurthy ,  Jinglun Eugene Tam ,  Geoffrey S. Gongwer ,  James Fahey, Jr. ,  Neal Berger ,  William Saiki

IPC分类号： G11C16/02 ,  G11C16/10 ,  H04N21/435 ,  H04N21/4405 ,  G11C8/00

CPC分类号： G11C16/10

摘要： Bulk operation logic circuitry for use in carrying out bulk program, erase, verify and margining operations on nonvolatile memory cells of a PLD, FPGA, flash-based microcontroller, EEPROM, flash memory device or other integrated circuit containing such cells includes a flag register for designating one or more selected blocks of cells to which the bulk operation will be limited. The bulk operation circuitry includes a controller, with a state machine and associated control logic, that distributes system clock signals and provides control signals to an instruction register, the flag register, an address register and one or more data registers to control loading of instructions and data into those registers through a serial input. The state machine is responsive to a mode signal for switching it from a normal user state into a bulk operation state. The use of a flag register allows simplification of the instruction set to register load instructions and basic bulk operation instructions (and a flow through operation using a serial output from the registers), while providing a wide variety of possible block selections for the different bulk operations.

摘要翻译： 用于在PLD，FPGA，基于闪存的微控制器，EEPROM，闪速存储器件或包含这种单元的其它集成电路的非易失性存储器单元上执行批量编程，擦除，验证和裕度操作的批量操作逻辑电路包括：标志寄存器 指定将限制批量操作的一个或多个选定的单元块。 大容量操作电路包括具有状态机和相关联的控制逻辑的控制器，其分配系统时钟信号并向控制寄存器，标志寄存器，地址寄存器和一个或多个数据寄存器提供控制信号，以控制指令的加载，以及 通过串行输入将数据写入这些寄存器。 状态机响应于将模式信号从正常用户状态切换到大容量操作状态。 使用标志寄存器可以简化寄存器加载指令和基本批量操作指令（以及使用寄存器的串行输出的操作流程）的指令集，同时为不同的批量操作提供各种可能的块选择 。