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    One transistor DRAM device and method of forming the same
    11.
    发明授权
    One transistor DRAM device and method of forming the same 有权
    一种晶体管DRAM器件及其形成方法

    公开(公告)号：US07795651B2

    公开(公告)日：2010-09-14

    申请号：US12024459

    申请日：2008-02-01

    申请人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    发明人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    IPC分类号： H01L31/112

    CPC分类号： H01L27/10802 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

    摘要： A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.

    摘要翻译： 一个晶体管DRAM器件包括：具有绝缘层的衬底，设置在绝缘层上的第一半导体层，包括与绝缘层接触的第一源极区域和第一区域以及第一源极 区域和第一漏极区域，覆盖第一浮动体的第一栅极图案，覆盖第一栅极图案的第一层间电介质，设置在第一层间电介质上并包括第二源极区域和第二漏极区域的第二半导体层 其与第一层间电介质接触，第二浮动体与第二源极区和第二漏极区之间接触，第二栅极图案覆盖第二浮体。

    Methods of forming one transistor DRAM devices
    13.
    发明授权
    Methods of forming one transistor DRAM devices 有权
    形成一个晶体管DRAM器件的方法

    公开(公告)号：US08168530B2

    公开(公告)日：2012-05-01

    申请号：US12842703

    申请日：2010-07-23

    申请人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    发明人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/10802 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

    摘要： A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.

    摘要翻译： 一个晶体管DRAM器件包括：具有绝缘层的衬底，设置在绝缘层上的第一半导体层，包括与绝缘层接触的第一源极区域和第一区域以及第一源极 区域和第一漏极区域，覆盖第一浮动体的第一栅极图案，覆盖第一栅极图案的第一层间电介质，设置在第一层间电介质上并包括第二源极区域和第二漏极区域的第二半导体层 其与第一层间电介质接触，第二浮动体与第二源极区和第二漏极区之间接触，第二栅极图案覆盖第二浮体。

    Memory device including 3-dimensionally arranged memory cell transistors and methods of operating the same
    14.
    发明授权
    Memory device including 3-dimensionally arranged memory cell transistors and methods of operating the same 有权
    包括三维布置的存储单元晶体管的存储器件及其操作方法

    公开(公告)号：US07701771B2

    公开(公告)日：2010-04-20

    申请号：US11882769

    申请日：2007-08-06

    申请人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Hoo-Sung Cho

    发明人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Hoo-Sung Cho

    IPC分类号： G11C11/03

    CPC分类号： H01L27/115 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551

    摘要： A memory device may include L semiconductor layers, a gate structure on each of the semiconductor layers, N bitlines, and/or a common source line on each of the semiconductor layers. The L semiconductor layers may be stacked, and/or L may be an integer greater than 1. The N bitlines may be on the gate structures and crossing over the gate structures, and/or N may be an integer greater than 1. Each of the common source lines may be connected to each other such that the common source lines have equipotentiality with each other.

    摘要翻译： 存储器件可以包括L个半导体层，每个半导体层上的栅极结构，N个位线和/或每个半导体层上的公共源极线。 L个半导体层可以被堆叠，和/或L可以是大于1的整数.N个位线可以在栅极结构上并且跨过栅极结构，和/或N可以是大于1的整数。 公共源极线可以彼此连接，使得公共源极线彼此具有等电位。

    Multi-layer memory devices
    16.
    发明授权
    Multi-layer memory devices 有权
    多层存储设备

    公开(公告)号：US08258563B2

    公开(公告)日：2012-09-04

    申请号：US13049495

    申请日：2011-03-16

    申请人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    发明人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    IPC分类号： H01L29/76

    CPC分类号： H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    摘要： A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

    摘要翻译： 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。

    Multilevel integrated circuit devices and methods of forming the same
    17.
    发明授权
    Multilevel integrated circuit devices and methods of forming the same 有权
    多层集成电路器件及其形成方法

    公开(公告)号：US07586135B2

    公开(公告)日：2009-09-08

    申请号：US11606569

    申请日：2006-11-30

    申请人： Wook-Hyun Kwon ,  Ki-Nam Kim ,  Chan-Kwang Park ,  Soon-Moon Jung ,  Sang-Pil Sim

    发明人： Wook-Hyun Kwon ,  Ki-Nam Kim ,  Chan-Kwang Park ,  Soon-Moon Jung ,  Sang-Pil Sim

    IPC分类号： H01L29/80

    CPC分类号： H01L27/0688 ,  H01L21/8221

    摘要： Semiconductor devices including a plurality of semiconductor layers. A plurality of transistors are on each of the semiconductor layers. The transistors include gate lines and have source regions and drain regions formed between the gate lines in the respective semiconductor layer including the transistors. The semiconductor devices further include a plurality of local source line structures. Each of the local source line structures is positioned on a corresponding one of the semiconductor layers and connects a plurality of the source regions formed on the corresponding one of the semiconductor layers. Methods of forming the semiconductor devices are also provided.

    摘要翻译： 包括多个半导体层的半导体器件。 多个晶体管位于每个半导体层上。 晶体管包括栅极线，并且在包括晶体管的相应半导体层中的栅极线之间形成源极区和漏极区。 半导体器件还包括多个本地源极线结构。 局部源极线结构中的每一个位于相应的一个半导体层上，并连接形成在相应一个半导体层上的多个源极区。 还提供了形成半导体器件的方法。

    Multi-layer nonvolatile memory devices and methods of fabricating the same
    19.
    发明申请
    Multi-layer nonvolatile memory devices and methods of fabricating the same 审中-公开
    多层非易失性存储器件及其制造方法

    公开(公告)号：US20080108213A1

    公开(公告)日：2008-05-08

    申请号：US11654133

    申请日：2007-01-17

    申请人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    发明人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    IPC分类号： H01L21/4763 ,  H01L21/3205

    CPC分类号： H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

    摘要： A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

    摘要翻译： 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。

    NAND flash memory device with 3-dimensionally arranged memory cell transistors
    20.
    发明申请
    NAND flash memory device with 3-dimensionally arranged memory cell transistors 审中-公开
    具有三维排列的存储单元晶体管的NAND闪存器件

    公开(公告)号：US20080067554A1

    公开(公告)日：2008-03-20

    申请号：US11705163

    申请日：2007-02-12

    申请人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    发明人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    IPC分类号： H01L29/76

    CPC分类号： H01L27/115 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11551

    摘要： A NAND flash memory device includes a plurality of stacked semiconductor layers, device isolation layer patterns disposed in predetermined regions of each of the plurality of semiconductor layers, the device isolation layers defining active regions, source and drain impurity regions in the active regions, a source line plug structure electrically connecting the source impurity regions, and a bit-line plug structure electrically connecting the drain impurity regions, wherein the source impurity regions are electrically connected to the semiconductor layers.

    摘要翻译： NAND闪速存储器件包括多个层叠的半导体层，设置在多个半导体层中的每一个的预定区域中的器件隔离层图案，器件隔离层限定有源区域，有源区域中的源极和漏极杂质区域，源极 电连接源杂质区的线插头结构，以及电连接漏极杂质区的位线插头结构，其中源杂质区电连接到半导体层。