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    AUTOMATED SENSITIVITY DEFINITION AND CALIBRATION FOR DESIGN FOR MANUFACTURING TOOLS
    12.
    发明申请
    AUTOMATED SENSITIVITY DEFINITION AND CALIBRATION FOR DESIGN FOR MANUFACTURING TOOLS 有权
    用于制造工具的自动灵敏度定义和校准

    公开(公告)号：US20110166686A1

    公开(公告)日：2011-07-07

    申请号：US12652409

    申请日：2010-01-05

    Applicant: James A. Culp ,  Jason D. Hibbeler ,  Lars W. Liebmann ,  Tina Wagner

    Inventor： James A. Culp ,  Jason D. Hibbeler ,  Lars W. Liebmann ,  Tina Wagner

    IPC: G06F17/50 ,  G06G7/66 ,  G06N5/02

    CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A method of automatic calibration of a design for manufacturing (DfM) simulation tool includes providing, as a first input, one or more defined rules for each of one or more semiconductor device levels to be simulated by the tool, and providing, as a second input, a plurality of defined feature size threshold ranges and increments for use in histogram generation of a number of failures with respect to a reference circuit; providing, as a third input, the reference circuit; executing the defined rules for the semiconductor device levels to be simulated, and outputting a fail count for the reference circuit at each defined threshold value, thereby generating histogram data of fail count versus threshold for the reference circuit; and providing, as a fourth input, a defined fail count metric, thereby calibrating the DfM tool for use with respect to a target circuit.

    Abstract translation: 一种用于制造设计（DfM）模拟工具的自动校准的方法包括为由工具模拟的一个或多个半导体器件级别中的每一个提供一个或多个限定规则作为第一输入，并且作为第二输入提供第二 输入，多个定义的特征尺寸阈值范围和增量，用于相对于参考电路的多个故障的直方图生成; 提供参考电路作为第三输入; 执行要被模拟的半导体器件电平的限定规则，并在每个定义的阈值处输出参考电路的故障计数，由此产生参考电路的故障计数与阈值的直方图数据; 并且作为第四输入提供定义的故障计数度量，从而校准用于目标电路的DfM工具。

    Method for verification of resolution enhancement techniques and optical proximity correction in lithography
    14.
    发明授权
    Method for verification of resolution enhancement techniques and optical proximity correction in lithography 失效
    用于光刻中分辨率增强技术和光学邻近校正的验证方法

    公开(公告)号：US06996797B1

    公开(公告)日：2006-02-07

    申请号：US10904600

    申请日：2004-11-18

    Applicant: Lars W. Liebmann ,  James A. Culp ,  Ioana C. Graur ,  Maharaj Mukherjee

    Inventor： Lars W. Liebmann ,  James A. Culp ,  Ioana C. Graur ,  Maharaj Mukherjee

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G03F1/36 ,  G06F2217/12 ,  Y02P90/265

    Abstract: A method for model-based verification of resolution enhancement techniques (RET) and optical proximity correction (OPC) in lithography includes scaling shapes of a drawn mask layout to their corresponding intended wafer dimensions so as to create a scaled image. A first feature of the scaled image is shifted with respect to a second feature thereof in accordance with a predetermined maximum overlay error. An intersection parameter of the first and said second features of the scaled image is calculated so as to determine a yield metric of an ideal layout. A first feature of a simulated wafer image is shifted with respect to a second feature thereof in accordance with the predetermined maximum overlay error. An intersection parameter of the first and said second features of the simulated wafer image is calculated so as to determine a yield metric of a simulated layout, and the yield metric of the simulated wafer image is compared to the yield metric of the scaled image.

    Abstract translation: 用于光刻中的分辨率增强技术（RET）和光学邻近校正（OPC）的基于模型的验证的方法包括将绘制的掩模布局的形状缩放到其相应的预期晶片尺寸，以便创建缩放图像。 根据预定的最大重叠误差，缩放图像的第一特征相对于其第二特征偏移。 计算缩放图像的第一和第二特征的交点参数，以便确定理想布局的屈服度量。 模拟晶片图像的第一特征相对于其第二特征根据预定的最大重叠误差而偏移。 计算模拟晶片图像的第一和第二特征的交叉参数，以便确定模拟布局的屈服度量，并将模拟晶片图像的屈服度量与缩放图像的屈服度量进行比较。

    METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD
    15.
    发明申请
    METHODS AND SYSTEM FOR ANALYSIS AND MANAGEMENT OF PARAMETRIC YIELD 有权
    参数化分析与管理方法与系统

    公开(公告)号：US20120227019A1

    公开(公告)日：2012-09-06

    申请号：US13471789

    申请日：2012-05-15

    Applicant: James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

    Inventor： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

    IPC: G06F17/50

    CPC classification number: G01R31/26 ,  G06F17/5045

    Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

    Abstract translation: 对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。 设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。 可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。 此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

    Multilayer OPC for design aware manufacturing
    16.
    发明授权
    Multilayer OPC for design aware manufacturing 有权
    多层OPC用于设计感知制造

    公开(公告)号：US08214770B2

    公开(公告)日：2012-07-03

    申请号：US12357648

    申请日：2009-01-22

    Applicant: Maharaj Mukherjee ,  James A. Culp ,  Lars Liebmann ,  Scott M. Mansfield

    Inventor： Maharaj Mukherjee ,  James A. Culp ,  Lars Liebmann ,  Scott M. Mansfield

    IPC: G06F17/50

    CPC classification number: G03F1/36

    Abstract: A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.

    Abstract translation: 提供了一种用于设计用于集成电路的掩模布局的方法，其通过在晶片上包括功能层间和层内约束来确保电路特征之间的适当的功能交互。 根据本发明使用的功能约束应用于模拟晶片图像中，以确保正确的功能交互，同时放松或消除对晶片图像的位置的EPE约束。

    ANALYZING MULTIPLE INDUCED SYSTEMATIC AND STATISTICAL LAYOUT DEPENDENT EFFECTS ON CIRCUIT PERFORMANCE
    17.
    发明申请
    ANALYZING MULTIPLE INDUCED SYSTEMATIC AND STATISTICAL LAYOUT DEPENDENT EFFECTS ON CIRCUIT PERFORMANCE 失效
    分析多种诱导系统和统计布局对电路性能的依赖性影响

    公开(公告)号：US20120144356A1

    公开(公告)日：2012-06-07

    申请号：US13371537

    申请日：2012-02-13

    Applicant: Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

    Inventor： Shayak Banerjee ,  Dureseti Chidambarrao ,  James A. Culp ,  Praveen Elakkumanan ,  Saibal Mukhopadhyay

    IPC: G06F9/455

    CPC classification number: G06F17/5009 ,  G06F2217/10

    Abstract: A method for implementing systematic, variation-aware integrated circuit extraction includes inputting a set of processing conditions to a plurality of variation models, each model corresponding to a separate systematic, parametric variation associated with semiconductor manufacturing of an integrated circuit layout; generating, for each variation model, a netlist update attributable to the associated variation, wherein the netlist update is an update with respect to an original netlist extracted from the integrated circuit layout; and storing the netlist updates generated for each of the processing conditions.

    Abstract translation: 一种用于实现系统的变异感知集成电路提取的方法包括：将一组处理条件输入到多个变化模型，每个模型对应于与集成电路布局的半导体制造相关联的单独的系统参数变化; 针对每个变化模型生成归因于相关变化的网表更新，其中网表更新是相对于从集成电路布局提取的原始网表的更新; 以及存储针对每个处理条件生成的网表更新。

    Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells
    19.
    发明授权
    Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells 有权
    基于单个电池的已知多晶硅周边密度布置集成电路设计的方法

    公开(公告)号：US07890906B2

    公开(公告)日：2011-02-15

    申请号：US12117761

    申请日：2008-05-09

    Applicant: Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

    Inventor： Laura S. Chadwick ,  James A. Culp ,  David J. Hathaway ,  Anthony D. Polson

    IPC: G06F17/50

    CPC classification number: G06F17/5068

    Abstract: Disclosed is a method of laying out individual cells of an integrated circuit design, based at least in part on the known polysilicon perimeter densities of those cells. That is, the method embodiments use the knowledge of polysilicon perimeter density for known cells to drive placement of those cells on a chip (i.e., to drive floor-planning). The method embodiments can be used to achieve approximately uniform across-chip polysilicon perimeter density and, thereby to limit performance parameter variations between functional devices that are attributable to variations in polysilicon perimeter density. Alternatively, the method embodiments can be used to selectively control variations in the average polysilicon perimeter density of different regions of a chip and, thereby to selectively control certain performance parameter variations between functional devices located in those different regions.

    Abstract translation: 公开了至少部分地基于这些单元的已知多晶硅周边密度来布置集成电路设计的单个单元的方法。 也就是说，方法实施例使用已知单元的多晶硅周密度的知识来驱动这些单元在芯片上的放置（即，驱动楼层规划）。 方法实施例可以用于实现大致均匀的跨芯片多晶硅周边密度，并且由此限制可归因于多晶硅周边密度变化的功能器件之间的性能参数变化。 或者，方法实施例可以用于选择性地控制芯片的不同区域的平均多晶硅周长密度的变化，从而选择性地控制位于那些不同区域中的功能设备之间的某些性能参数变化。

    Integrated circuit with uniform polysilicon perimeter density, method and design structure
    20.
    发明授权
    Integrated circuit with uniform polysilicon perimeter density, method and design structure 有权
    具有均匀多晶硅周密度的集成电路，方法和设计结构

    公开(公告)号：US07849433B2

    公开(公告)日：2010-12-07

    申请号：US12117771

    申请日：2008-05-09

    Applicant: Laura S. Chadwick ,  James A. Culp ,  David J Hathaway ,  Anthony D. Polson

    Inventor： Laura S. Chadwick ,  James A. Culp ,  David J Hathaway ,  Anthony D. Polson

    IPC: G06F17/50

    CPC classification number: H01L27/0207 ,  G06F17/5072

    Abstract: Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve the desired decoupling capacitance. Then, local polysilicon perimeter densities of the blocks are determined and, as necessary, the decoupling capacitor blocks are reconfigured in order to adjust for differences in the local polysilicon perimeter densities. This reconfiguring is performed in a manner that essentially maintains the desired decoupling capacitance. Due to the across-chip polysilicon perimeter density uniformity, functional devices in different regions of the chip will exhibit limited performance parameter variations (e.g., limited threshold voltage variations). Also disclosed herein are embodiments of an integrated circuit structure formed according to the method embodiments and a design structure for the integrated circuit.

    Abstract translation: 公开了形成具有期望的去耦电容并具有均匀和目标的跨芯片多晶硅周长密度的集成电路的实施例。 该方法包括根据设计布置功能块以形成电路，并且还布置一个或多个去耦电容器块以实现期望的去耦电容。 然后，确定块的局部多晶硅周边密度，并且根据需要重新配置去耦电容器块，以便调整局部多晶硅周边密度的差异。 这种重新配置以基本维持期望的去耦电容的方式执行。 由于跨芯片多晶硅周边密度均匀性，芯片的不同区域中的功能器件将表现出有限的性能参数变化（例如，限制阈值电压变化）。 本文还公开了根据方法实施例形成的集成电路结构和集成电路的设计结构的实施例。

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